Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits

2002 ◽  
Author(s):  
M.J. Ohletz
Keyword(s):  
Fault Simulation ◽  
Cmos Circuits ◽  
Mapping Scheme

Fault simulation of unconventional faults in CMOS circuits

1991 ◽  
Vol 10 (5) ◽  
pp. 677-682 ◽  
Author(s):  
M. Favalli ◽  
P. Olivo ◽  
M. Damiani ◽  
B. Ricco
Keyword(s):  
Fault Simulation ◽  
Cmos Circuits

My-box representation for faulty CMOS circuits

1990 ◽  
Vol 137 (3) ◽  
pp. 225 ◽  
Author(s):  
J.-E. Chen ◽  
C.L. Lee ◽  
W.-Z. Shen
Keyword(s):  
Cmos Circuits

Analysis of Oversampling Effect on Selected Mapping Scheme Using CORR Metric

2016 ◽  
Vol E99.B (2) ◽  
pp. 364-369
Author(s):  
Jun-Young WOO ◽  
Kee-Hoon KIM ◽  
Kang-Seok LEE ◽  
Jong-Seon NO ◽  
Dong-Joon SHIN
Keyword(s):  
Mapping Scheme

A Manual Diagnosis Approach Using Targeted Fault Injection and Fault Simulation to Extend ATPG Diagnostic Resolution in Localizing Faults

2019 ◽  
Author(s):  
Rommel Estores ◽  
Karo Vander Gucht
Keyword(s):  
Fault Injection ◽  
Fault Simulation ◽  
Fault Localization ◽  
Pattern Generation ◽  
Test Coverage ◽  
Actual Case ◽  
Electrical Failure ◽  
Starting Point ◽  
Diagnostic Resolution ◽  
Diagnosis Approach

Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.

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