Efficient O(√n) BIST algorithms for DDNPS faults in dual port memories

Abstract The conventional methods for testing the Dual Port Random Access Memories (DPRAM) may not be suitable for the Three-Dimensional Integrated Circuit (3-D IC) structures, due to their limited test vectors with heterogeneous integration. This paper takes an Application Specific Integrated Chips (ASIC) approach to gain some insight into the Front-end behavioral testing and backend routability of the dual port memories with complex Serial Advanced Technology Attachment (Serial-ATA) design, in a 3-D IC structure. The presented implementation used commercially available Dual Port memories from the two different vendors. The commercially available DesignWare Advanced Host Controller Interface (SATA/AHCI), which is based on the SATA 2.6 AHCI host and external SATA (eSATA) standard bus architecture, with My_foundry’s 14nm low power process (14lp) technologies for the logical and physical implementations. The methodology evaluates the memory quality and performance/characteristics, in terms of timing, power and area. This paper shows memory testing in both implementation/verification in a readily built-up SATA test environment.

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A VLSI processor-switch for a dual IEEE-796 bus with shared and dual-port memories

Proceedings. VLSI and Computer Peripherals. COMPEURO 89 ◽

10.1109/cmpeur.1989.93461 ◽

2003 ◽

Author(s):

J. Opsommer ◽

E.H. D'Hollander

Keyword(s):

Dual Port Memories

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New fault models and efficient BIST algorithms for dual-port memories

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.658567 ◽

1997 ◽

Vol 16 (9) ◽

pp. 987-1000

Author(s):

A.A. Amin ◽

M.Y. Osman ◽

R.E. Abdel-Aal ◽

H. Al-Muhtaseb

Keyword(s):

Fault Models ◽

Dual Port Memories

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An Alternative Test Method for the Dual Port SRAM Memory through the Designware SATA AHCI Implementation in 3-D IC Structures

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) ◽

10.2174/2352096514666211214092852 ◽

2021 ◽

Vol 14 ◽

Author(s):

Chandrashekhar Virupakshagouda Patil ◽

Suma Suryanarayana Suryanarayana

Keyword(s):

Integrated Circuit ◽

Three Dimensional ◽

Test Method ◽

Advanced Technology ◽

Process Technology ◽

Test Environment ◽

Test Methodology ◽

Serial Advanced Technology Attachment ◽

Test Vectors ◽

Dual Port Memories

Background: It is being considered that conventional methods for testing the dual port memories might not be suitable for the Three-Dimensional Integrated Circuit (3-D IC) structures due to the presence of the limited test vectors with heterogeneous integration. Objective: Find out a novel test methodology DPRAMs in 3-D IC structures. Methods: This paper has taken the approach called as Application Specific Integrated Chips(ASIC) to gain insights on Front-End behavioral testing and Back-End routability of the dual port memories integrated with complex Serial Advanced Technology Attachment (Serial-ATA) design, in a 3-D IC structure. The presented implementation is using commercially available dual port memories from two different vendors. The commercially available DesignWare Advanced Host Controller Interface (SATA/AHCI) is based on the Serial Advanced Technology Attachment (SATA 2.6), AHCI host and external SATA (eSATA) standard bus architecture and being used with My_foundry’s 14nm Low Power (14LP) process technology for logical and physical implementations. Results: This paper shows memory testing in both implementation/verification in a readily built-up SATA test environment. Conclusion: It is being considered that the approach described here might be used as a tool/environment for evaluating any vendor's DPRAMs/2Ports RAMs/2Ports Register Files. As a result, it offers an alternative to the traditional test methodology.

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