Sequential logic synthesis for testability using register-transfer level descriptions

Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool

2012 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2012.6419110 ◽

2012 ◽

Author(s):

Tsuyoshi Iwagaki ◽

Takehiro Mikami ◽

Hideyuki Ichihara ◽

Tomoo Inoue

Keyword(s):

Logic Synthesis ◽

Register Transfer Level ◽

Circuit Optimization ◽

Synthesis Tool ◽

Register Transfer ◽

False Paths

Download Full-text

Standard for Verilog register transfer level synthesis

10.3403/30128339u ◽

2015 ◽

Keyword(s):

Register Transfer Level ◽

Register Transfer

Download Full-text

Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level

International Journal of VLSI Design & Communication Systems ◽

10.5121/vlsic.2011.2406 ◽

2011 ◽

Vol 2 (4) ◽

pp. 61-68

Author(s):

M S Suma

Keyword(s):

Fault Modeling ◽

Register Transfer Level ◽

Sequential Circuits ◽

Register Transfer ◽

Combinational And Sequential Circuits

Download Full-text

Incorporating the controller effects during register transfer level synthesis

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC ◽

10.1109/edtc.1994.326916 ◽

2002 ◽

Cited By ~ 4

Author(s):

C. Ramachandran ◽

F.J. Kurdahi

Keyword(s):

Register Transfer Level ◽

Register Transfer

Download Full-text

A non-scan DFT method at register-transfer level to achieve complete fault efficiency

Proceedings of the 2000 conference on Asia South Pacific design automation - ASP-DAC '00 ◽

10.1145/368434.368825 ◽

2000 ◽

Cited By ~ 12

Author(s):

Satoshi Ohtake ◽

Hiroki Wada ◽

Toshimitsu Masuzawa ◽

Hideo Fujiwara

Keyword(s):

Dft Method ◽

Register Transfer Level ◽

Register Transfer

Download Full-text

Test pattern generators for distributed and embedded built-in self-test at register transfer level

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design ◽

10.1109/isqed.2001.915236 ◽

2002 ◽

Author(s):

V. Vorisek

Keyword(s):

Test Pattern ◽

Register Transfer Level ◽

Register Transfer ◽

Self Test ◽

Built In Self Test ◽

Pattern Generators

Download Full-text

Implicit state transition graphs: applications to sequential logic synthesis and test

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers ◽

10.1109/iccad.1990.129847 ◽

2002 ◽

Cited By ~ 11

Author(s):

P. Ashar ◽

A. Ghosh ◽

S. Devadas ◽

A.R. Newton

Keyword(s):

State Transition ◽

Logic Synthesis ◽

Sequential Logic ◽

Transition Graphs

Download Full-text

A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level

10.1109/dac18074.2021.9586248 ◽

2021 ◽

Author(s):

Johannes Muller ◽

Mohammad Rahmani Fadiheh ◽

Anna Lena Duque Anton ◽

Thomas Eisenbarth ◽

Dominik Stoffel ◽

...

Keyword(s):

Register Transfer Level ◽

Formal Approach ◽

Register Transfer

Download Full-text

A Register Transfer Level Approach for Intermittent Semi-Concurrent Error Detection

2010 2nd International Conference on E-business and Information System Security ◽

10.1109/ebiss.2010.5473579 ◽

2010 ◽

Author(s):

Donghu Yang ◽

Jianhui Jiang ◽

Jie Yin ◽

Jipeng Huang

Keyword(s):

Error Detection ◽

Register Transfer Level ◽

Concurrent Error Detection ◽

Register Transfer

Download Full-text

Efficient Digital System Design Methodology with SystemC Register Transfer Level Modeling

IEEE SoutheastCon, 2004. Proceedings. ◽

10.1109/secon.2004.1287966 ◽

2004 ◽

Author(s):

M.C. Zabawa ◽

S.V. Wunnava

Keyword(s):

System Design ◽

Design Methodology ◽

Register Transfer Level ◽

Digital System ◽

Register Transfer ◽

Digital System Design

Download Full-text