Transient Submodeling Analysis for Board-Level Drop Tests of Electronic Packages

2007 ◽  
Vol 30 (1) ◽  
pp. 54-62 ◽  
Author(s):  
Tsung-Yueh Tsai ◽  
Chang-Lin Yeh ◽  
Yi-Shao Lai ◽  
Rong-Sheng Chen
Keyword(s):  
Electronic Packages ◽  
Drop Tests ◽  
Board Level

Accelerated Thermal Cycling Guidelines for Electronic Packages in Military Avionics Thermal Environment

2004 ◽  
Vol 126 (2) ◽  
pp. 256-264 ◽  
Author(s):  
Raghuram V. Pucha ◽  
Krishna Tunga ◽  
James Pyland ◽  
Suresh K. Sitaraman
Keyword(s):  
Thermal Cycling ◽  
Thermal Environment ◽  
Inelastic Strain ◽  
Electronic Packages ◽  
Strain Accumulation ◽  
Material Models ◽  
Process Mechanics ◽  
Accelerated Thermal Cycling ◽  
Damage Mapping ◽  
Board Level

A field-use induced damage mapping methodology is presented that can take into consideration the field-use thermal environment profile to develop accelerated thermal cycling guidelines for packages intended to be used in military avionics thermal environment. The board-level assembly process mechanics and critical geometric features with appropriate material models are taken into consideration while developing the methodology. The models developed are validated against in-house and published accelerated thermal cycling experimental data. The developed mapping methodology is employed to design alternate accelerated thermal cycles by matching the creep and plastic strain contributions to total inelastic strain accumulation in solder under military field-use and accelerated thermal cycling environments, while reducing the time for accelerated thermal cycling and qualification.

High-Speed Cyclic Bend Tests and Board-Level Drop Tests for Evaluating the Robustness of Solder Joints in Printed Circuit Board Assemblies

2009 ◽  
Vol 38 (6) ◽  
pp. 884-895 ◽  
Author(s):  
E.H. Wong ◽  
S.K.W. Seah ◽  
C.S. Selvanayagam ◽  
R. Rajoo ◽  
W.D. van Driel ◽  
...  
Keyword(s):  
High Speed ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Printed Circuit ◽  
Drop Tests ◽  
Bend Tests ◽  
Board Level

Modelling the Influence of Conformal Coatings on Thermo-Mechanical Fatigue of Solder Interconnects in Electronic Packages

2018 ◽  
Vol 2018 (HiTEC) ◽  
pp. 000007-000014 ◽  
Author(s):  
Maxim Serebreni ◽  
Ross Wilcoxon ◽  
F. Patrick McCluskey
Keyword(s):  
System Level ◽  
Electronic Packages ◽  
Temperature Dependent ◽  
Coating Materials ◽  
Conformal Coating ◽  
Solder Interconnects ◽  
Wide Range ◽  
Conformal Coatings ◽  
Temperature Dependent Properties ◽  
Board Level

Abstract Protecting electronic components at harsh environments and applications often requires the use of conformal coatings, underfills or potting compounds. The temperature dependent properties of these materials greatly depend on their chemical formulation. Conformal coatings used for electronic applications are available in a variety of materials ranging from silicones, acrylics, polyurethanes, paralyne and epoxies. The glass transition temperature (Tg) varies for each material and represents a phase change from a hard glassy one to a soft rubbery state. Temperature fluctuations experienced by electronics can span a wide range that can often include the Tg of the encapsulant. In this paper, thermal cycling simulations are performed on QFN and BGA components using different conformal coating materials. Material characterization is performed to determine the temperature dependent properties of several conformal coating materials. Results illustrate higher damage accumulation during ramp down and cold side of thermal cycles. Information obtained in this study is used to develop a mitigation strategy that enables selection of encapsulants without compromising desired system level encapsulation method to increase overall board level reliability.

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