A simple model of emi-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

M.P. Robinson; K. Fischer; I.D. Flintoft; A.C. Marvin

doi:10.1109/temc.2003.815529

A simple model of emi-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

IEEE Transactions on Electromagnetic Compatibility ◽

10.1109/temc.2003.815529 ◽

2003 ◽

Vol 45 (3) ◽

pp. 513-519 ◽

Cited By ~ 25

Author(s):

M.P. Robinson ◽

K. Fischer ◽

I.D. Flintoft ◽

A.C. Marvin

Keyword(s):

Simple Model ◽

Digital Circuits ◽

Statistical Distribution ◽

Timing Jitter ◽

Circuit Performance

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SPICESoft: AUTOMATED TOOL FOR SENSITIVITY ANALYSIS, PERFORMANCE ANALYSIS, AND INVERSE PERFORMANCE ANALYSIS OF DIGITAL CIRCUITS

Journal of Circuits System and Computers ◽

10.1142/s0218126608004319 ◽

2008 ◽

Vol 17 (02) ◽

pp. 221-238

Author(s):

K. S. YEO ◽

Z. H. KONG

Keyword(s):

Sensitivity Analysis ◽

Performance Analysis ◽

Digital Circuits ◽

Circuit Analysis ◽

Analysis Tool ◽

Circuit Performance ◽

Simulation Results ◽

Differential Expansion ◽

The Relationship ◽

Automated Tool

An automated circuit analysis tool called SPICESoft, the main objective of which is to help designers in sensitivity computation and circuit analysis is presented. Three main features of SPICESoft are described, namely Sensitivity Analysis, Circuit Performance Analysis, and Inverse Circuit Performance Analysis. A new methodology called Binary Differential Expansion used for data interpolation is also described in this paper. The relationship between device and process parameters is covered. The simulation results obtained using the proposed automated tool are compared with those of conventional computation.

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Regulated Charge Pumps: A Comparative Study by Means of Verilog-AMS

Electronics ◽

10.3390/electronics9060998 ◽

2020 ◽

Vol 9 (6) ◽

pp. 998 ◽

Cited By ~ 3

Author(s):

Andrea Ballo ◽

Michele Bottaro ◽

Alfio Dario Grasso ◽

Gaetano Palumbo

Keyword(s):

Simple Model ◽

Comparative Study ◽

Digital Circuits ◽

Charge Pump ◽

Electronic Systems ◽

Behavioral Models ◽

Charge Pumps ◽

Analog And Digital Circuits ◽

Simulation Time ◽

Good Agreement

This paper proposes a comparative study of regulation schemes for charge-pump-based voltage generators using behavioral models in Verilog- Analog Mixed Signal (AMS) code. An accurate and simple model of the charge pump is first introduced. It allows reducing the simulation time of complex electronic systems made up by both analog and digital circuits while maintaining a good agreement with transistor-level simulations. Finally, a comprehensive comparative study of the different regulation schemes for charge pumps is reported which allows the designer to choose the most suitable topology for a given application and Charge Pump (CP) operative zone.

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Optimization of CNFET Parameters for High Performance Digital Circuits

Advances in Materials Science and Engineering ◽

10.1155/2016/6303725 ◽

2016 ◽

Vol 2016 ◽

pp. 1-9 ◽

Cited By ~ 7

Author(s):

Shimaa Ibrahim Sayed ◽

Mostafa Mamdouh Abutaleb ◽

Zaki Bassuoni Nossair

Keyword(s):

High Performance ◽

Design Methodology ◽

Digital Circuits ◽

Digital Circuit ◽

Operating Voltage ◽

Circuit Performance ◽

Contact Materials ◽

Strong Candidate ◽

Power Delay Product ◽

Near Future

The Carbon Nanotube Field Effect Transistor (CNFET) is one of the most promising candidates to become successor of silicon CMOS in the near future because of its better electrostatics and higher mobility. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This paper presents a study that investigates the effect of different CNFET parameters on performance and proposes a new CNFET design methodology to optimize performance characteristics such as current driving capability, delay, power consumption, and area for digital circuits. We investigate and conceptually explain the performance measures at 32 nm technologies for pure-CNFET, hybrid MOS-CNFET, and CMOS configurations. In our proposed design methodology, the power delay product (PDP) of the optimized CNFET is about 68%, 63%, and 79% less than that of the nonoptimized CNFET, hybrid MOS-CNFET, and CMOS circuits, respectively. Therefore, the proposed CNFET design is a strong candidate to implement high performance digital circuits.

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Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis

VLSI Design ◽

10.1080/1065514021000012264 ◽

2002 ◽

Vol 15 (3) ◽

pp. 647-666 ◽

Cited By ~ 1

Author(s):

Tong Xiao ◽

Malgorzata Marek-Sadowska

Keyword(s):

Digital Circuits ◽

Timing Analysis ◽

Deep Submicron ◽

Functional Information ◽

Slew Rate ◽

Static Timing Analysis ◽

Circuit Performance ◽

Arrival Times ◽

Static Timing ◽

Functional Correlation

Crosstalk-induced delay in deep sub-micron digital circuits can be quite significant and difficult to determine because of dependency on neighboring signals. In this paper we study the problem of incorporating temporal and functional information to improve the accuracy of crosstalk aware static timing analysis. We propose an efficient method to compute a signal's earliest and latest arrival times when timing windows and slew rate ranges are known for its inputs and its coupling neighbors' inputs. We show that iteratively updating timing windows is necessary when signals on the same path are mutually coupled. The accuracy of static timing analysis can be further improved by our functional correlation analysis. The proposed techniques have been applied in crosstalk aware static timing analysis, which can guide timing-driven layout synthesis and quick timing verification in deep submicron technologies. Experimental results demonstrate that the proposed methods significantly reduce the pessimism in predicting circuit performance.

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