Influence of Body Effect on Sample-and-Hold Circuit Design Using Negative Capacitance FET

2018 ◽  
Vol 65 (9) ◽  
pp. 3909-3914 ◽  
Author(s):  
Yuhua Liang ◽  
Xueqing Li ◽  
Sumitha George ◽  
Srivatsa Srinivasa ◽  
Zhangming Zhu ◽  
...  
Keyword(s):  
Circuit Design ◽  
Negative Capacitance ◽  
Body Effect ◽  
Sample And Hold

A 2-Port Stable Negative Capacitance Circuit Design With Unilateral Gain Boosting Technique

2017 ◽  
Vol 65 (12) ◽  
pp. 4953-4959 ◽  
Author(s):  
Ngoc-Duy-Hien Lai ◽  
Nhut-Tan Doan ◽  
Hyoungsoo Kim ◽  
Sang-Woong Yoon
Keyword(s):  
Circuit Design ◽  
Negative Capacitance ◽  
Boosting Technique

scholarly journals Bulk Bias as an Analog Single-Event Transient Mitigation Technique with Negligible Penalty

Electronics ◽  
2019 ◽  
Vol 9 (1) ◽  
pp. 27
Author(s):  
Jingtian Liu ◽  
Qian Sun ◽  
Bin Liang ◽  
Jianjun Chen ◽  
Yaqing Chi ◽  
...  
Keyword(s):  
Circuit Design ◽  
Analog Circuits ◽  
Analog Circuit ◽  
Forward Bias ◽  
Cmos Technology ◽  
Common Source ◽  
Single Event ◽  
Single Event Transient ◽  
Body Effect ◽  
Radiation Hardened

In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.

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