Embedding Statistical Variability Into Propagation Delay Time Compact Models Using Different Parameter Sets: A Comparative Study in 35-nm Technology

2018 ◽  
Vol 65 (7) ◽  
pp. 2714-2720 ◽  
Author(s):  
Hamed Jooypa ◽  
Daryoosh Dideban
Keyword(s):  
Comparative Study ◽  
Delay Time ◽  
Propagation Delay ◽  
Propagation Delay Time ◽  
Compact Models ◽  
Statistical Variability

scholarly journals Quaternary regenerative CMOS logic circuits with high-impedance output state

2005 ◽  
Vol 18 (3) ◽  
pp. 505-514
Author(s):  
Dusanka Bundalo ◽  
Branimir Ðordjevic ◽  
Zlatko Bundalo
Keyword(s):  
Computer Simulation ◽  
Computer Simulations ◽  
Delay Time ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Output State ◽  
High Impedance ◽  
Multiple Valued Logic ◽  
Propagation Delay Time ◽  
Simulation Results

Principles and possibilities of synthesis and design of quaternary multiple valued regenerative CMOS logic circuits with high-impedance output state are de- scribed and proposed in the paper. Two principles of synthesis and implementation of CMOS regenerative quaternary multiple-valued logic circuits with high-impedance output state are proposed and described: the simple circuits with smaller number of transistors, and the buffer/driver circuits with decreased propagation delay time. The schemes of such logic circuits are given and analyzed by computer simulations. Some of computer simulation results confirming descriptions and conclusions are also given in the paper.

scholarly journals Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

Crystals ◽  
2021 ◽  
Vol 11 (9) ◽  
pp. 1150
Author(s):  
Yoanlys Hernandez ◽  
Bernhard Stampfer ◽  
Tibor Grasser ◽  
Michael Waltl
Keyword(s):  
Delay Time ◽  
Propagation Delay ◽  
Operating Conditions ◽  
Physical Models ◽  
Stable Operation ◽  
Reliability Models ◽  
Bias Temperature Instability ◽  
Propagation Delay Time ◽  
Aging Mechanisms ◽  
The Impact

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

scholarly journals PERANCANGAN DIVIDER 8-BIT DENGAN TEKNOLOGI 180NM MENGGUNAKAN PERANGKAT LUNAK ELECTRIC

TRANSIENT ◽  
2017 ◽  
Vol 6 (3) ◽  
pp. 411
Author(s):  
Rizko Prasada Fitriansyah ◽  
Munawar Agus Riyadi ◽  
Muhammad Arfan
Keyword(s):  
Delay Time ◽  
Propagation Delay ◽  
Area Coverage ◽  
Propagation Delay Time ◽  
Arithmetic Logic Unit ◽  
Timing Delay ◽  
Logic Unit

Operasi pembagian merupakan salah satu operasi penting yang ada pada blok Arithmetic Logic Unit (ALU). Meskipun operasi pembagian lebih jarang digunakan jika dibandingkan dengan penjumlahan dan perkalian, lamanya waktu yang dibutuhkan untuk menyelesaikan operasi ini menyebabkan banyak energi yang terbuang. Untuk mengatasi permasalahan tersebut, terdapat beberapa teknik yang dapat dilakukan, salah satunya adalah dengan memilih algoritma yang tepat sehingga operasi yang dilakukan juga semakin cepat. Pada penelitian ini, dirancang sebuah divider menggunakan teknologi 180nm dengan algoritma non-restoring. Dalam penerapannya, digunakan perangkat lunak Electric untuk merancang layout dan LTspice untuk menguji fungsional serta melakukan pengukuran timing delay. Dari perancangan yang dilakukan, didapati divider ini memiliki luas sebesar 0,027mm2, propagation delay time sebesar 3,644ns, dan area coverage sebesar 45,975%.

Influences of nonuniformity in metal concentration in gate dielectric silicate on CMIS inverters' propagation delay time

2004 ◽  
Vol 48 (12) ◽  
pp. 2191-2198 ◽  
Author(s):  
Mizuki Ono ◽  
Tsunehiro Ino ◽  
Masato Koyama ◽  
Akira Takashima ◽  
Akira Nishiyama
Keyword(s):  
Metal Concentration ◽  
Delay Time ◽  
Gate Dielectric ◽  
Propagation Delay ◽  
Propagation Delay Time
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