Modeling of the Lateral Emitter-Current Crowding Effect in SiGe HBTs

2016 ◽  
Vol 63 (11) ◽  
pp. 4160-4166 ◽  
Author(s):  
Shon Yadav ◽  
Anjan Chakravorty ◽  
Michael Schroter
2002 ◽  
Vol 46 (11) ◽  
pp. 1997-2000 ◽  
Author(s):  
Yuchun Chang ◽  
Guotong Du ◽  
Junfeng Song ◽  
Songxin Wang ◽  
Hailin Luo ◽  
...  

2018 ◽  
Vol 32 (15) ◽  
pp. 1850157 ◽  
Author(s):  
Yue-Gie Liaw ◽  
Chii-Wen Chen ◽  
Wen-Shiang Liao ◽  
Mu-Chun Wang ◽  
Xuecheng Zou

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of [Formula: see text]–[Formula: see text] characteristics, threshold voltage [Formula: see text], and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance [Formula: see text], channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance [Formula: see text] and drive current.


2021 ◽  
Author(s):  
Paul O. Leisher ◽  
Michelle Labrecque ◽  
Kevin McClune ◽  
Elliot Burke ◽  
Daniel Renner ◽  
...  

2013 ◽  
Vol 34 (8) ◽  
pp. 1051-1056
Author(s):  
吴艳艳 WU Yan-yan ◽  
冯士维 FENG Shi-wei ◽  
乔彦斌 QIAO Yan-bin ◽  
魏光华 WEI Guang-hua ◽  
张建伟 ZHANG Jian-wei

2002 ◽  
Vol 91 (10) ◽  
pp. 8783 ◽  
Author(s):  
Jian Chen ◽  
Yun Li ◽  
Janusz Nowak ◽  
Juan Fernandez de-Castro

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