Influence of a Barrier Layer on the Formation of AuBe Ohmic Contact With the p-GaAs Bases of Heterojunction Bipolar Transistors

2011 ◽  
Vol 58 (8) ◽  
pp. 2582-2588 ◽  
Author(s):  
Qingzhou Xu Xu ◽  
Li-Wu Yang
1994 ◽  
Vol 08 (16) ◽  
pp. 2221-2243
Author(s):  
F. REN

Process technologies for self-aligned AlGaAs/GaAs and InGaP/GaAs heterojunction bipolar transistors (HBTs) as well as gate definition and dry etching fabrication schemes for submicron gate length AlGaAs/GaAs-based field effect transistors (FETs) are presented. Multiple energy F + and H + ions were used to isolate the active devices for HBTs. The resistance of test wafers at 200° C showed no change over periods of more than 50 days. Highly selective dry and wet etch techniques for InGaP/GaAs and AlGaAs/GaAs material systems were used to uniformly expose heterojunctions. Reliability of the alloyed ohmic contact and feasibility of the nonalloyed ohmic contact metallizations for both p and n type GaAs layers will be discussed. The reproducible gate recess etching is one of the critical steps for AlGaAs/GaAs-based FETs. The etching selectivity, damage, pre- and post-clean procedures were studied in terms of device performance. A simple low temperature SiN x deposition and an etch-back process with optical stepper were used to demonstrate 0.1 µm Y-shape gate feature.


1994 ◽  
Vol 33 (Part 1, No. 1B) ◽  
pp. 786-789 ◽  
Author(s):  
Tohru Sugiyama ◽  
Yasuhiko Kuriyama ◽  
Masayuki Asaka ◽  
Norio Iizuka ◽  
Torakichi Kobayashi ◽  
...  

1997 ◽  
Vol 71 (13) ◽  
pp. 1854-1856 ◽  
Author(s):  
Il-Ho Kim ◽  
Sung Ho Park ◽  
Tae-Woo Lee ◽  
Moon-Pyung Park

1993 ◽  
Vol 300 ◽  
Author(s):  
F. Ren

ABSTRACTProcess technologies for self-aligned AlGaAs/GaAs and lnGaP/GaAs heterojunction bipolar transistors (HBTs) as well as dry etching fabrication schemes for submicron AlGaAs/GaAs based field effect transistors (FETs) are presented. Multiple energy F+ and H+ ions were used to isolate the active devices for HBTs. The resistance of test wafers at 200 °C showed no change over periods of 50 days. Highly selective dry and wet etch techniques for InGaP/GaAs and AlGaAs/GaAs material systems were used to uniformly expose junctions. Reliability of the alloyed ohmic contact and feasibility of the non-alloyed ohmic contact metallizations for both p and n type GaAs layers will be discussed. The reproducible gate recess etching is one of the critical steps for AlGaAs/GaAs based FETs. The etching selectivity, damage, pre and post-clean procedure were studied in terms of device performance. A simple low temperature SiNx deposition and an etch-back process with optical stepper were used to demonstrate 0.1 μm Y-shape gate feature.


ChemInform ◽  
1990 ◽  
Vol 21 (30) ◽  
Author(s):  
C. DUBON-CHEVALLIER ◽  
P. BLANCONNIER ◽  
C. BESOMBES ◽  
C. MAYEUX ◽  
J. F. BRESSE ◽  
...  

1986 ◽  
Vol 59 (11) ◽  
pp. 3783-3786 ◽  
Author(s):  
C. Dubon‐Chevallier ◽  
M. Gauneau ◽  
J. F. Bresse ◽  
A. Izrael ◽  
D. Ankri

1990 ◽  
Vol 137 (5) ◽  
pp. 1514-1519 ◽  
Author(s):  
C. Dubon‐Chevallier ◽  
P. Blanconnier ◽  
C. Besombes ◽  
C. Mayeux ◽  
J. F. Bresse ◽  
...  

Author(s):  
N. David Theodore ◽  
Mamoru Tomozane ◽  
Ming Liaw

There is extensive interest in SiGe for use in heterojunction bipolar transistors. SiGe/Si superlattices are also of interest because of their potential for use in infrared detectors and field-effect transistors. The processing required for these materials is quite compatible with existing silicon technology. However, before SiGe can be used extensively for devices, there is a need to understand and then control the origin and behavior of defects in the materials. The present study was aimed at investigating the structural quality of, and the behavior of defects in, graded SiGe layers grown by chemical vapor deposition (CVD).The structures investigated in this study consisted of Si1-xGex[x=0.16]/Si1-xGex[x= 0.14, 0.13, 0.12, 0.10, 0.09, 0.07, 0.05, 0.04, 0.005, 0]/epi-Si/substrate heterolayers grown by CVD. The Si1-xGex layers were isochronally grown [t = 0.4 minutes per layer], with gas-flow rates being adjusted to control composition. Cross-section TEM specimens were prepared in the 110 geometry. These were then analyzed using two-beam bright-field, dark-field and weak-beam images. A JEOL JEM 200CX transmission electron microscope was used, operating at 200 kV.


Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.


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