Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

2008 ◽  
Vol 55 (7) ◽  
pp. 1614-1620 ◽  
Author(s):  
Masaya Kawano ◽  
Nobuaki Takahashi ◽  
Yoichiro Kurita ◽  
Koji Soejima ◽  
Masahiro Komuro ◽  
...  
Keyword(s):  
Data Transfer ◽  
Three Dimensional ◽  
Packaging Technology

Wafer Level Assembly Technique Development for Fine Pitch Flip Chip 3D Die-to-Wafer Integration

2010 ◽  
Vol 2010 (1) ◽  
pp. 000548-000553
Author(s):  
Zhaozhi Li ◽  
Brian J. Lewis ◽  
Paul N. Houston ◽  
Daniel F. Baldwin ◽  
Eugene A. Stout ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Three Dimensional ◽  
Cost Effective ◽  
Market Demand ◽  
Wafer Level ◽  
Packaging Technology ◽  
Fine Pitch ◽  
3D Packaging ◽  
Assembly Technique

Three Dimensional (3D) Packaging has become an industry obsession as the market demand continues to grow toward higher packaging densities and smaller form factor. In the meanwhile, the 3D die-to-wafer (D2W) packaging structure is gaining popularity due to its high manufacturing throughput and low cost per package. In this paper, the development of the assembly process for a 3D die-to-wafer packaging technology, that leverages the wafer level assembly technique and flip chip process, is introduced. Research efforts were focused on the high-density flip chip wafer level assembly techniques, as well as the challenges, innovations and solutions associated with this type of 3D packaging technology. Processing challenges and innovations addressed include flip chip fluxing methods for very fine-pitch and small bump sizes; wafer level flip chip assembly program creation and yield improvements; and set up of the Pb-free reflow profile for the assembled wafer. 100% yield was achieved on the test vehicle wafer that has totally 1,876 flip chip dies assembled on it. This work has demonstrated that the flip chip 3D die-to-wafer packaging architecture can be processed with robust yield and high manufacturing throughput, and thus to be a cost effective, rapid time to market alternative to emerging 3D wafer level integration methodologies.

scholarly journals THE PROPERTIES OF GEOMETRICALLY MODELLING COMPUTATIONAL SCHEMES FOR BUILDING STRUCTURES

2021 ◽  
Vol 12 (1) ◽  
pp. 32-38
Author(s):  
Vladimir Popov ◽  
Eduard Kriksunov ◽  
Tatjana Grigorjeva
Keyword(s):  
Computational Model ◽  
Data Exchange ◽  
Data Transfer ◽  
Three Dimensional ◽  
Integrated Design ◽  
Integrated Analysis ◽  
Building Structures ◽  
Structural Behaviour ◽  
Actual Structure ◽  
Developmental Features

For launching a project on a structural object, the calculation of building structures stands as one of the most important stages of project development. In order to correctly analyse structural behaviour, determine the stress-strain state and solve design or inspection problems, the designer is forced to adequately formalize the actual structure turning it into a faultless computational scheme. Virtual testing is one of the main features of the single graphical-information model. Interoperable systems for three-dimensional modelling and analysis, calculation and design ensure smooth data transfer between the physical and computational model. Modern object-modelling techniques and integrated analysis systems allow achieving the defined goal. The article deals with the forms of data exchange, the developmental features of the designed and computational (analysis) BIM model, the integrated design process of CAD/CAE as well as the conversion problems of the physical and computational model.

Robust Watermarking of Polygonal Meshes Based on Vertex Norms Variance Distortion

2017 ◽  
Vol 25 (4) ◽  
pp. 46-60 ◽  
Author(s):  
Yesmine Ben Amar ◽  
Imen Trabelsi ◽  
Nilanjan Dey ◽  
Fuqian Shi ◽  
Suresh Chandra Satapathy ◽  
...  
Keyword(s):  
Copyright Protection ◽  
Data Transfer ◽  
Three Dimensional ◽  
Blind Detection ◽  
Robust Watermarking ◽  
Polygonal Meshes ◽  
Detection Scheme ◽  
Media Type ◽  
Digital Contents

The three-dimensional (3D) mesh is moderately novel media type that realizes a rising success in various applications through data transfer via the Internet, which requires security approaches. Technological copyright protection of digital contents has become a challenging task in the current digital epoch. In this work, a robust watermarking algorithm of polygonal meshes for copyright protection purposes is proposed. The watermark insertion was achieved by quantization of the vertex norms variance in order to insert the watermark bits. In addition, this method is based on a blind detection scheme, so the watermark can be extracted without referring to the original mesh. The experimental results established the quality of the watermarked object as well as the inserted watermark robustness against various types of attacks, which were evaluated to prove the validity of the proposed algorithm. The results proved the proposed method efficiency in terms of robustness and imperceptibility against several signal processing distortions. A comparison with other reported method with similar purposes is also provided. The comparison depicted the outstanding robustness of the proposed method compared to the other reported method.

Optically Coupled Three-Dimensional Common Memory with Novel Data Transfer Method

1989 ◽  
Vol 28 (Part 2, No. 12) ◽  
pp. L2305-L2308 ◽  
Author(s):  
Hirokazu Takata ◽  
Hiroki Mori ◽  
Junichiro Iba ◽  
Mitsumasa Koyanagi
Keyword(s):  
Data Transfer ◽  
Three Dimensional ◽  
Transfer Method ◽  
Common Memory

A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer

2006 ◽  
Author(s):  
M. Kawano ◽  
S. Uchiyama ◽  
Y. Egawa ◽  
N. Takahashi ◽  
Y. Kurita ◽  
...  
Keyword(s):  
Data Transfer ◽  
Packaging Technology ◽  
3D Packaging

Producibility in the Naval Ship Design Process: A Progress Report

1993 ◽  
Vol 9 (04) ◽  
pp. 210-223
Author(s):  
Robert G. Keane ◽  
Howard Fireman
Keyword(s):  
Design Process ◽  
Data Transfer ◽  
Three Dimensional ◽  
Ship Design ◽  
Digital Data ◽  
Cost Models ◽  
Total Quality ◽  
Improvement Project ◽  
Design Engineers ◽  
Naval Ship

In October 1989, A Ship Design for Producibility Workshop was held by the Naval Sea Systems Command (NAVSEA) at the David Taylor Research Center (DTRC). The purpose of the workshop was "To develop the framework of a plan to integrate producibility concepts and processes into the NAVSEA Ship Design Process." The major recommendations of the workshop included initiatives related to increased training of NAVSEA design engineers in modern ship production concepts, development of producibility design tools and practices for use by NAVSEA design engineers, improved cost models, implementation of producibility strategies for ship design process improvements, modification to existing acquisition practices, and improved three-dimensional (3-D) digital data transfer. The workshop was one of NAVSEA's first Total Quality Leadership (TQL) initiatives and was subsequently expanded into the Ship Design, Acquisition and Construction (DAC) Process Improvement Project. This paper reports on the major findings and recommendations of the workshop, the near term accomplishments since the workshop, and the long range strategic plan for continuously improving producibility in the Naval Ship Design Process.

A Hybrid Optimization Based on GPU Parallel Computing Method and its Application of Three Dimensional Large Eddy Simulations

2013 ◽  
Vol 275-277 ◽  
pp. 2589-2594 ◽  
Author(s):  
Yu Xuan Zhang ◽  
Song Ping Wu
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Three Dimensional ◽  
Processing Unit ◽  
Desktop Computer ◽  
Central Processing ◽  
Eddy Simulation ◽  
Turbulence Flow ◽  
Large Eddy ◽  
Optimization Schemes

Using compute Unified device architecture (CUDA), a traditional computational fluid dynamics (CFD) program is paralleled and optimized based on graphic processing unit (GPU). The calculation process is divided into two parts as serial and parallel. Their main characteristics are analyzed and different optimization schemes are given. CPU (central processing unit) and GPU work respectively as flow control and high-speed parallel computation. Bandwidth between devices is applied effectively. Data transfer between devices is moderately improved to simplify algorithm. Finally, the method is verified by simulating a three-dimensional isotropic homogeneous turbulence flow field. The calculation uses large eddy simulation (LES) method with secondary filter and solves the three-dimensional N-S equations. The maximum grid number achieves 8,000,000 and takes 33 seconds each step. All calculations are using ordinary single desktop computer, optimized acceleration ratio can reach 9.

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