Strained CMOS Devices With Shallow-Trench-Isolation Stress Buffer Layers

2008 ◽  
Vol 55 (4) ◽  
pp. 1085-1089 ◽  
Author(s):  
Yiming Li ◽  
Hung-Ming Chen ◽  
Shao-Ming Yu ◽  
Jiunn-Ren Hwang ◽  
Fu-Liang Yang
Keyword(s):  
Buffer Layers ◽  
Shallow Trench Isolation ◽  
Isolation Stress ◽  
Trench Isolation ◽  
Stress Buffer

Shallow Trench Isolation Stress Effect on NMOS Transistor Leakage, SRAM Standby Current and VCCMIN

2019 ◽  
Vol 18 (1) ◽  
pp. 117-122
Author(s):  
Jianhua Ju ◽  
Eric Liu ◽  
Zhaoxu Shen ◽  
Allan Zhou ◽  
Jinhua Liu ◽  
...  
Keyword(s):  
Stress Effect ◽  
Nmos Transistor ◽  
Shallow Trench Isolation ◽  
Isolation Stress ◽  
Trench Isolation

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

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