Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- $\kappa$ Gate Dielectrics

2009 ◽  
Vol 56 (1) ◽  
pp. 100-108 ◽  
Author(s):  
Martin Schlosser ◽  
Krishna K. Bhuwalka ◽  
Martin Sauter ◽  
Thomas Zilbauer ◽  
Torsten Sulima ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Dielectrics ◽  
Drain Current ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

scholarly journals Design Optimization of Nanotube Tunnel Field-Effect Transistor with Bias-Induced Electron-Hole Bilayer

2021 ◽  
Author(s):  
Xueke Wang ◽  
Yabin Sun ◽  
Ziyu Liu ◽  
Yun Liu ◽  
Xiaojin Li ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Dynamic Performance ◽  
Drain Current ◽  
Electron Hole ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
And Performance ◽  
First Time ◽  
Tcad Simulations

Abstract In this paper, a novel nanotube tunneling field-effect transistor (NT-TFET) with bias-induced electron-hole bilayer (EHBNT-TFET) is proposed for the first time. By the intentional misalignment and an asymmetric bias configuration of the inner-gate and outer-gate, the line tunneling takes place inside the channel, significantly improving the tunneling rate and area. The device principle and performance are investigated by calibrated 3-D TCAD simulations. Compared to the conventional NT-TFET, the proposed EHBNT-TFET exhibits an increased ON-state current (ION) about 57.2 times and a sub-60 mV/dec subthreshold swing for seven orders of magnitude of drain current. Furthermore, the increased ION and reduced gate capacitance achieve improved dynamic performance. Compared with conventional NT-TFET, the intrinsic delay decreased about 142 times is obtained in EHBNT-TFET.

scholarly journals Drain Current Model for a Single Gate Tunnel Field Effect Transistor with Hetero-Dielectric Gate (HDG)

2021 ◽  
Author(s):  
AJAY Kumar SINGH ◽  
Tan Chun Fui ◽  
Lim Way Soong
Keyword(s):  
Closed Form ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Current Model ◽  
Tunneling Current ◽  
Drain Current ◽  
Analytical Models ◽  
Potential Candidate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract Purpose: A TFET (Tunnel Field Effect Transistor) is a potential candidate to replace CMOS in deep-submicron region due to its lower SS (subthreshold swing, <60 mV/decade) at room temperature. However, the conventional TFET suffers from low tunneling current and high ambipolar current. To overcome these two drawbacks a new structure, known as Hetero-dielectric gate TFET (HDG TFET), has been proposed in the literature. Method: To analyze the electrical characteristics of this structure, a closed form of analytical expression of current is required. This paper presents the closed form of compact analytical current model for HDG TFET structure without using any iterative method. Result: The developed compact analytical models show a good agreement with 2-D TCAD simulator results. The model is used to study in depth about the electrical behavior of the device under various physical variation as well as bias variation. Conclusion: The proposed model can be incorporated into SPICE to describe the behavior of HDG TFET faster.

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