Electrical Characteristics of Memory Devices With a High-$k$$\hbox{HfO}_{2}$ Trapping Layer and Dual $\hbox{SiO}_{2}/\hbox{Si}_{3}\hbox{N}_{4}$ Tunneling Layer

2007 ◽  
Vol 54 (10) ◽  
pp. 2699-2705 ◽  
Author(s):  
Ying Qian Wang ◽  
Wan Sik Hwang ◽  
Gang Zhang ◽  
G. Samudra ◽  
Yee-Chia Yeo ◽  
...  
2019 ◽  
Vol 11 (4) ◽  
pp. 04005-1-04005-5 ◽  
Author(s):  
Varra Reddy ◽  
◽  
D. V. Vivekananda ◽  
G. Sai Krishna ◽  
B. Sri Vivek ◽  
...  

2015 ◽  
Vol 51 (28) ◽  
pp. 6130-6132 ◽  
Author(s):  
Lyubov A. Frolova ◽  
Pavel A. Troshin ◽  
Diana K. Susarova ◽  
Alexander V. Kulikov ◽  
Nataliya A. Sanina ◽  
...  

Memory devices with superior electrical characteristics were designed using an interfacial spirooxazine layer introduced between dielectric and semiconductor layers in OFETs.


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