A Novel Nanoscaled Device Concept: Quasi-SOI MOSFET to Eliminate the Potential Weaknesses of UTB SOI MOSFET

2005 ◽  
Vol 52 (4) ◽  
pp. 561-568 ◽  
Author(s):  
Y. Tian ◽  
R. Huang ◽  
X. Zhang ◽  
Y. Wang
Keyword(s):  
Soi Mosfet ◽  
Utb Soi Mosfet

Characteristic Variations Induced by Random Fluctuation of Source/Drain Lateral Distribution Dopant in Nano-Scale UTB SOI MOSFET

2019 ◽  
Vol 18 (1) ◽  
pp. 77-81
Author(s):  
Linfeng Du ◽  
Hui Deng ◽  
Gang Du ◽  
Ruqi Han ◽  
Shengdong Zhang
Keyword(s):  
Lateral Distribution ◽  
Random Fluctuation ◽  
Soi Mosfet ◽  
Nano Scale ◽  
Utb Soi Mosfet

scholarly journals The impact of high-k dielectrics on the performance of Schottky barrier source/drain (SBSD) ultra-thin body (UTB) SOI MOSFET

2008 ◽  
Vol 57 (7) ◽  
pp. 4476
Author(s):  
Luan Su-Zhen ◽  
Liu Hong-Xia ◽  
Jia Ren-Xu ◽  
Cai Nai-Qiong ◽  
Wang Jin
Keyword(s):  
Schottky Barrier ◽  
Thin Body ◽  
Soi Mosfet ◽  
High K ◽  
Utb Soi Mosfet ◽  
The Impact

scholarly journals Impact of Structural Aspect, Metal Gate and Channel Material on UTB-SOI-MOSFET

2019 ◽  
Vol 9 (1) ◽  
pp. 1638-1642
Keyword(s):  
Field Effect Transistors ◽  
Silicon Film ◽  
Structural Aspect ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Thin Body ◽  
Metal Gate ◽  
Short Channel ◽  
Soi Mosfet ◽  
Utb Soi Mosfet

Ultra Thin Body Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistors (UTB-SOI-MOSFETs) provide better immunity to Short Channel Effects (SCEs). But the behaviour changes at miniaturization and still the many unexplored effects need to be analysied. Here in this paper, Drain Induced Barrier Lowering (DIBL) and sub-threshold Slope (SS) variation of a n-channel UTB-SOI-MOSFET have been analyzed by changing the device structural aspects like gate length (LG), BOX thickness (tBOX) and Silicon film thickness (tSi). Also, the effect of intrinsic parameters as metal gate work function and channel material variation on DIBL and sub-threshold Slope (SS) variation has been analyzed

Recessed source/drain for sub-50 nm UTB SOI MOSFET

2007 ◽  
Vol 22 (5) ◽  
pp. 577-583 ◽  
Author(s):  
Wei Ke ◽  
Xu Han ◽  
Dingyu Li ◽  
Xinan Wang ◽  
Tianyi Zhang ◽  
...  
Keyword(s):  
Soi Mosfet ◽  
Utb Soi Mosfet

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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