Impact of interfacial layer and transition region on gate current performance for high-K gate dielectric stack: its tradeoff with gate capacitance

2003 ◽  
Vol 50 (2) ◽  
pp. 433-439 ◽  
Author(s):  
Yang-Yu Fan ◽  
Qi Xiang ◽  
J. An ◽  
L.F. Register ◽  
S.K. Banerjee
Keyword(s):  
Transition Region ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Gate Current ◽  
Gate Capacitance ◽  
High K ◽  
High K Gate Dielectric

High quality, high-k gate dielectric: amorphous LaAlO3 thin films grown on Si(100) without Si interfacial layer

2003 ◽  
Vol 77 (5) ◽  
pp. 721-724 ◽  
Author(s):  
L. Yan ◽  
H.B. Lu ◽  
G.T. Tan ◽  
F. Chen ◽  
Y.L. Zhou ◽  
...  
Keyword(s):  
Thin Films ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
High Quality ◽  
High K ◽  
High K Gate Dielectric

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

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