A pipelined 8-bit soft decision viterbi decoder for IEEE802.11ac WLAN systems

2012 ◽  
Vol 58 (4) ◽  
pp. 1162-1168 ◽  
Author(s):  
Wonsun Yoo ◽  
Yunho Jung ◽  
Moo Kim ◽  
Seongjoo Lee
2021 ◽  
Vol 8 (4) ◽  
pp. 1-25
Author(s):  
Saleh Khalaj Monfared ◽  
Omid Hajihassani ◽  
Vahid Mohsseni ◽  
Dara Rahmati ◽  
Saeid Gorgin

In this work, we present a novel bitsliced high-performance Viterbi algorithm suitable for high-throughput and data-intensive communication. A new column-major data representation scheme coupled with the bitsliced architecture is employed in our proposed Viterbi decoder that enables the maximum utilization of the parallel processing units in modern parallel accelerators. With the help of the proposed alteration of the data scheme, instead of the conventional bit-by-bit operations, 32-bit chunks of data are processed by each processing unit. This means that a single bitsliced parallel Viterbi decoder is capable of decoding 32 different chunks of data simultaneously. Here, the Viterbi’s Add-Compare-Select procedure is implemented with our proposed bitslicing technique, where it is shown that the bitsliced operations for the Viterbi internal functionalities are efficient in terms of their performance and complexity. We have achieved this level of high parallelism while keeping an acceptable bit error rate performance for our proposed methodology. Our suggested hard and soft-decision Viterbi decoder implementations on GPU platforms outperform the fastest previously proposed works by 4.3{\times } and 2.3{\times } , achieving 21.41 and 8.24 Gbps on Tesla V100, respectively.


Integration ◽  
2012 ◽  
Vol 45 (2) ◽  
pp. 132-140 ◽  
Author(s):  
Jaeseong Kim ◽  
Shingo Yoshizawa ◽  
Yoshikazu Miyanaga

2007 ◽  
Vol 31 (8) ◽  
pp. 529-536
Author(s):  
Chau Yun Hsu ◽  
Tsung Sheng Kuo ◽  
Yuan Hung Hsu

2013 ◽  
Author(s):  
Guixuan Liang ◽  
Jorge Portilla ◽  
Teresa Riesgo

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