A High Performance Soft Decision Viterbi Decoder for Wlan and Broadband Applications

2006 ◽  
Author(s):  
Abdul-rafeeq Abdul-Shakoor ◽  
Valek Szwarc
Keyword(s):  
High Performance ◽  
Viterbi Decoder ◽  
Soft Decision

A High-throughput Parallel Viterbi Algorithm via Bitslicing

2021 ◽  
Vol 8 (4) ◽  
pp. 1-25
Author(s):  
Saleh Khalaj Monfared ◽  
Omid Hajihassani ◽  
Vahid Mohsseni ◽  
Dara Rahmati ◽  
Saeid Gorgin
Keyword(s):  
High Throughput ◽  
High Performance ◽  
Viterbi Algorithm ◽  
Data Representation ◽  
Processing Unit ◽  
Viterbi Decoder ◽  
Soft Decision ◽  
Content Type ◽  
Data Intensive ◽  
Representation Scheme

In this work, we present a novel bitsliced high-performance Viterbi algorithm suitable for high-throughput and data-intensive communication. A new column-major data representation scheme coupled with the bitsliced architecture is employed in our proposed Viterbi decoder that enables the maximum utilization of the parallel processing units in modern parallel accelerators. With the help of the proposed alteration of the data scheme, instead of the conventional bit-by-bit operations, 32-bit chunks of data are processed by each processing unit. This means that a single bitsliced parallel Viterbi decoder is capable of decoding 32 different chunks of data simultaneously. Here, the Viterbi’s Add-Compare-Select procedure is implemented with our proposed bitslicing technique, where it is shown that the bitsliced operations for the Viterbi internal functionalities are efficient in terms of their performance and complexity. We have achieved this level of high parallelism while keeping an acceptable bit error rate performance for our proposed methodology. Our suggested hard and soft-decision Viterbi decoder implementations on GPU platforms outperform the fastest previously proposed works by 4.3{\times } and 2.3{\times } , achieving 21.41 and 8.24 Gbps on Tesla V100, respectively.

scholarly journals High performance ACS for Viterbi decoder using pipeline T-Algorithm

2015 ◽  
Vol 54 (3) ◽  
pp. 447-455 ◽  
Author(s):  
D. Vaithiyanathan ◽  
J. Nargis ◽  
R. Seshasayanan
Keyword(s):  
High Performance ◽  
Viterbi Decoder

High performance Viterbi decoder design

2018 ◽  
Vol 22 (S3) ◽  
pp. 7063-7068
Author(s):  
V. Kavitha ◽  
S. Mohanraj
Keyword(s):  
High Performance ◽  
Viterbi Decoder ◽  
Decoder Design

A pipelined 8-bit soft decision viterbi decoder for IEEE802.11ac WLAN systems

2012 ◽  
Vol 58 (4) ◽  
pp. 1162-1168 ◽  
Author(s):  
Wonsun Yoo ◽  
Yunho Jung ◽  
Moo Kim ◽  
Seongjoo Lee
Keyword(s):  
Viterbi Decoder ◽  
Soft Decision

scholarly journals An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
T. Kalavathi Devi ◽  
Sakthivel Palaniappan
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Forward Error Correction ◽  
Vlsi Architecture ◽  
Convolutional Codes ◽  
Viterbi Decoder ◽  
Asynchronous Design

Convolutional codes are comprehensively used as Forward Error Correction (FEC) codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI) templates, namely, Precharge Half Buffer (PCHB) and Weak Conditioned Half Buffer (WCHB). The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

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