Fatigue and Bridging Study of High-Aspect-Ratio Multicopper-Column Flip-Chip Interconnects Through Solder Joint Shape Modeling

2006 ◽  
Vol 29 (3) ◽  
pp. 560-569 ◽  
Author(s):  
E.B. Liao ◽  
A.A.O. Tay ◽  
S.S.T. Ang ◽  
H.H. Feng ◽  
R. Nagarajan ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
Solder Joint ◽  
High Aspect Ratio ◽  
Flip Chip ◽  
Shape Modeling ◽  
Joint Shape ◽  
Bridging Study

A Two-Body Formulation for Solder Joint Shape Prediction

1998 ◽  
Vol 120 (3) ◽  
pp. 302-308 ◽  
Author(s):  
F. P. Renken ◽  
G. Subbarayan
Keyword(s):  
Solder Joint ◽  
Surface Area ◽  
Flip Chip ◽  
Contact Angles ◽  
Sessile Droplet ◽  
Solution Approach ◽  
Shape Prediction ◽  
Body Formulation ◽  
Wetted Surface Area ◽  
Joint Shape

Solder shape prediction is essential for accurate fatigue life determination and joint design optimization. In the present paper, a new solution approach using the surface tension theory is developed to simultaneously predict standoff height, wetted surface area, contact angles, and solder shape by including energy effects between a molten solder body and an arbitrarily shaped solid body. Existing models for solder shape prediction do not appear to determine all characteristics including joint standoff height, wetted surface area, and contact angles simultaneously. A general two-body axisymmetric finite element code is developed and coupled with a constrained optimizer to solve four illustrative examples. These examples include the shape of a sessile droplet on a fixed pad, a flip-chip joint, a sessile droplet on a free surface, and a typical ceramic ball grid array solder joint. In all four examples, the results predicted by the present approach compare favorably with available experimental and numerical results.

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

2015 ◽  
Vol 2015 (1) ◽  
pp. 000793-000798
Author(s):  
Keith Best ◽  
Roger McCleary ◽  
Richard Hollman ◽  
Phillip Holmes
Keyword(s):  
Aspect Ratio ◽  
High Aspect Ratio ◽  
High Performance ◽  
Flip Chip ◽  
Technology Development ◽  
Semiconductor Industry ◽  
Scale Up ◽  
Wafer Level ◽  
Integration Schemes ◽  
Advanced Packaging

Advanced packaging technologies continue to enable the semiconductor industry to meet the needs for ever thinner, smaller and faster components required in mobile devices and other high performance applications. In the early days of advanced packaging, C4 solder bumps were the alternative to wire bonding. Although lead-free solder remains one of the preferred methods for assembly, tall copper structures (copper pillars) are becoming the standard interconnect solution for many applications. A process of lithography and subsequent electroplating are the mainstream process for today's copper pillar formation on wafer level for high-end flip chip devices. The latest trends in advanced packaging require another technology development when it comes to copper pillars. Modern integration schemes such as 2.5D interposer as well as 3D stacking have pushed the limits of standard lithography and copper electroplating capabilities. Specifically, the need for fine-pitch high aspect ratio copper pillars represents a challenge. In addition, the trend towards rectangular panel-based packaging as seen with glass interposers or panel fan-out (P-FO) devices demands a challenging scale-up of lithography and electroplating equipment and processing capabilities. This work specifically focuses on the formation of high-aspect ratio copper pillars in excess of 100μm by means of stepper-based lithography followed by electroplating. A unique test vehicle has been created to evaluate the process latitude for lithography for different resist materials as well as the specific electroplating challenges associated with these tall and narrow structures. The paper investigates the influence of key parameters such as CD uniformity, pattern density variations and resist profile on the critically important pillar height uniformity across the wafer or panel. In addition, the resist profile behavior at the substrate interface is being examined as it influences undercut behavior during wet etch of the plating seed layer. A number of wet and dry-film resist materials and appropriate lithography processes (spin coat or laminate, expose, develop) followed by copper plating based on varying chemistries and process parameters are being explored. The paper also summarizes the current requirements for the above mentioned lithography and plating processes as seen in the industry today.

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