The development of a hardware abstraction layer generator for system-on-chip functional verification

2010 VI Southern Programmable Logic Conference (SPL) ◽

10.1109/spl.2010.5483004 ◽

2010 ◽

Cited By ~ 1

Author(s):

Tiago Lins ◽

Edna Barros

Keyword(s):

System On Chip ◽

Functional Verification ◽

Abstraction Layer ◽

Hardware Abstraction Layer ◽

On Chip

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Property-driven functional verification technique for high-speed vision system-on-chip processor

Japanese Journal of Applied Physics ◽

10.7567/jjap.56.04cf15 ◽

2017 ◽

Vol 56 (4S) ◽

pp. 04CF15

Author(s):

Victor Nshunguyimfura ◽

Jie Yang ◽

Liyuan Liu ◽

Nanjian Wu

Keyword(s):

High Speed ◽

Vision System ◽

System On Chip ◽

Functional Verification ◽

On Chip

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The Use of UML Sequence Diagram for System-on-Chip System Level Transaction-based Functional Verification

2006 6th World Congress on Intelligent Control and Automation ◽

10.1109/wcica.2006.1714269 ◽

2006 ◽

Cited By ~ 8

Author(s):

JinShan Yu ◽

Tun Li ◽

QingPing Tan

Keyword(s):

System On Chip ◽

System Level ◽

Sequence Diagram ◽

Functional Verification ◽

On Chip ◽

Uml Sequence Diagram

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Automatic Test Generation From Semi-formal Specifications for Functional Verification of System-on-Chip Designs

2008 2nd Annual IEEE Systems Conference ◽

10.1109/systems.2008.4519044 ◽

2008 ◽

Cited By ~ 14

Author(s):

Christoph M. Kirchsteiger ◽

Johannes Grinschgl ◽

Christoph Trummer ◽

Christian Steger ◽

Reinhold Weiss ◽

...

Keyword(s):

Test Generation ◽

System On Chip ◽

Functional Verification ◽

Formal Specifications ◽

Automatic Test Generation ◽

Automatic Test ◽

On Chip

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A universal random test generator for functional verification of microprocessors and system-on-chip

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design ◽

10.1109/icvd.2005.37 ◽

2005 ◽

Cited By ~ 7

Author(s):

K. Uday Bhaskar ◽

M. Prasanth ◽

G. Chandramouli ◽

V. Kamakoti

Keyword(s):

System On Chip ◽

Functional Verification ◽

Random Test ◽

On Chip

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A Distributed Functional Verification Environment for the Design of System-on-Chip in Heterogeneous Architectures

2018 31st Symposium on Integrated Circuits and Systems Design (SBCCI) ◽

10.1109/sbcci.2018.8533247 ◽

2018 ◽

Author(s):

Thiago W B Silva ◽

Daniel C Morais ◽

Halamo G R Andrade ◽

Felipe C A Nunes ◽

Elmar Uwe Kurt Melcher ◽

...

Keyword(s):

System On Chip ◽

Functional Verification ◽

Heterogeneous Architectures ◽

On Chip

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Property-Driven Functional Verification Technique for High-Speed Vision System-on-Chip Processor

10.7567/ssdm.2016.ps-2-5-19 ◽

2016 ◽

Author(s):

V. Nshunguyimfura ◽

J. Yang ◽

L. Liu ◽

N. Wu

Keyword(s):

High Speed ◽

Vision System ◽

System On Chip ◽

Functional Verification ◽

On Chip

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Electronic System Level Models for Functional Verification of System-on-Chip

10.1109/cadsm.2007.4297576 ◽

2007 ◽

Cited By ~ 1

Author(s):

Alexander Adamov ◽

Karina Mostovaya ◽

Inna Syzonenko ◽

Alexey Melnik

Keyword(s):

Electronic System ◽

System On Chip ◽

System Level ◽

Functional Verification ◽

Electronic System Level ◽

On Chip

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Definition of a systematic method for the generation of software test programs allowing the functional verification of system on chip (SoC)

Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions ◽

10.1109/mtv.2003.1250257 ◽

2004 ◽

Cited By ~ 6

Author(s):

F. Hunsinger ◽

S. Francois ◽

A.A. Jerraya

Keyword(s):

System On Chip ◽

Software Test ◽

Functional Verification ◽

Systematic Method ◽

On Chip ◽

Definition Of

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Performance optimization on System on Chip using I²C Concept 6G Computer

International Innovative Research Journal of Engineering and Technology ◽

10.32595/iirjet.org/v1i4.2016.20 ◽

2016 ◽

Vol 1 (4) ◽

pp. 5-9

Author(s):

Kanimozhi D ◽

Karthikeyan P ◽

Kirthika S

Keyword(s):

Performance Optimization ◽

System On Chip ◽

On Chip

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Memory Implementation in a System on Chip with Built-in Self-Test and Recovery Tools

Proceedings of Universities ELECTRONICS ◽

10.24151/1561-5405-2019-24-3-239-247 ◽

2019 ◽

Vol 24 (3) ◽

pp. 239-247

Author(s):

Vladimir G. Ryabtsev ◽

◽

Sergey V. Volobuev ◽

Keyword(s):

System On Chip ◽

Self Test ◽

Built In Self Test ◽

On Chip ◽

Recovery Tools

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