Comparison of 0.25 μm bulk, PD and FD SOI CMOS implementations of a low-voltage low-power programmable DLL for linear delay generation

2002 ◽  
Author(s):  
P. Delatte ◽  
V. Brodeoux ◽  
P. Lorent ◽  
D. Flandre
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Linear Delay ◽  
Soi Cmos

Sub-0.25 μm ultra-thin SOI CMOS with a single N+ gate process for low-voltage and low-power applications

2002 ◽  
Author(s):  
C. Raynaud ◽  
O. Faynot ◽  
J.L. Pelloie ◽  
S. Tedesco ◽  
B. Ullmann ◽  
...  
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Soi Cmos

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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