scholarly journals Variation tolerant self-adaptive clock generation architecture based on a ring oscillator

2012 ◽  
Author(s):  
Jordi Perez-Puigdemont ◽  
Antonio Calomarde ◽  
Francesc Moll
Keyword(s):  
Ring Oscillator ◽  
Clock Generation ◽  
Self Adaptive

scholarly journals Design of High frequency Voltage Controlled Oscillators for Phase Locked Loop

2018 ◽  
Vol 7 (3.12) ◽  
pp. 871
Author(s):  
Thejusraj. H ◽  
Prithivi Raj ◽  
J Selvakumar ◽  
S Praveen Kumar
Keyword(s):  
Power Consumption ◽  
High Frequency ◽  
High Speed ◽  
Phase Locked Loop ◽  
Clock Recovery ◽  
Ring Oscillator ◽  
Voltage Controlled Oscillator ◽  
Voltage Controlled Oscillators ◽  
Clock Generation ◽  
Consumption Values

This paper presents the analysis of various oscillators that generate high frequency of oscillation for high speed communication, clock generation and clock recovery. The Ring oscillator and the Current Starved Voltage Controlled Oscillator(CSVCO) (for 5-stagewithout resistor and with resistor) have been implemented using the Cadence Virtuoso tool in 90 nm technology. The generated frequency of oscillation and the power consumption values of the voltage controlled oscillators have been calculated after inclusion in the PLL, and were also compared to identify the most suitable voltage controlled oscillator for a given application.

scholarly journals A Nano-Power 0.5 V Event-Driven Digital-LDO with Fast Start-Up Burst Oscillator for SoC-IoT

2020 ◽  
Vol 10 (4) ◽  
pp. 41
Author(s):  
Christos Konstantopoulos ◽  
Thomas Ussmueller
Keyword(s):  
Power Efficiency ◽  
High Gain ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Clock Generation ◽  
Start Up ◽  
Fast Start ◽  
Main Regulator ◽  
Gain Stage

Towards the integration of Digital-LDO regulators in the ultra-low-power System-On-Chip Internet-of-Things architecture, the D-LDO architecture should constitute the main regulator for powering digital and mixed-signal loads including the SoC system clock. Such an implementation requires an in-regulator clock generation unit that provides an autonomous D-LDO design. In contrast to contemporary D-LDO designs that employ ring-oscillator architecture which start-up time is dependent on the oscillating frequency, this work presents a design with nano-power consumption, fabricated with an active area of 0.035 mm2 at a 55-nm Global Foundries CMOS process that introduces a fast start-up burst oscillator based on a high-gain stage with wake-up time independent of D-LDO frequency. In combination with linear search coarse regulation and asynchronous fine regulation, it succeeds 558 nA minimum quiescent current with CL 75 pF, maximum current efficiency of 99.2% and 1.16x power efficiency improvement compared to analog counterpart oriented to SoC-IoT loads.

Low Frequency Ring Oscillator and Its Use in Non Overlapping Clock Generation

2012 ◽  
Vol 4 (6) ◽  
pp. 781-784
Author(s):  
Rishi Todani ◽  
Ashis Kumar Mal ◽  
Kanchan Baran Maji
Keyword(s):  
Low Frequency ◽  
Ring Oscillator ◽  
Clock Generation
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