Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

2011 ◽  
Author(s):  
Ye Lu ◽  
John McCanny ◽  
Sakir Sezer
Keyword(s):  
Virtual Channel ◽  
Networks On Chip ◽  
On Chip ◽  
Channel Architecture

Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip

2013 ◽  
Vol 29 (3) ◽  
pp. 431-452 ◽  
Author(s):  
Khalid Latif ◽  
Amir-Mohammad Rahmani ◽  
Ethiopia Nigussie ◽  
Tiberiu Seceleanu ◽  
Martin Radetzki ◽  
...  
Keyword(s):  
Fault Tolerance ◽  
Resource Management ◽  
Virtual Channel ◽  
Networks On Chip ◽  
On Chip

scholarly journals Low-Cost Allocator Implementations for Networks-on-Chip Routers

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-10
Author(s):  
Min Zhang ◽  
Chiu-Sing Choy
Keyword(s):  
Low Cost ◽  
Virtual Channel ◽  
Careful Study ◽  
Network Simulator ◽  
Networks On Chip ◽  
Look Ahead ◽  
Generic Architecture ◽  
On Chip ◽  
The Look ◽  
The Impact

Cost-effective Networks-on-Chip (NoCs) routers are important for future SoCs and embedded devices. Implementation results show that the generic virtual channel allocator (VA) and the generic switch allocator (SA) of a router consume large amount of area and power. In this paper, after a careful study of the working principle of a VA and the utilization statistics of its arbiters, opportunities to simplify the generic VA are identified. Then, the deadlock problem for a combined switch and virtual channel allocator (SVA) is studied. Next, the impact of the VA simplification on the router critical paths is analyzed. Finally, the generic architecture and two low-cost architectures proposed (the look-ahead, and the SVA) are evaluated with a cycle-accurate network simulator and detailed VLSI implementations. Results show that both the look-ahead and the SVA significantly reduce area and power compared to the generic architecture. Furthermore, cost savings are achieved without performance penalty.

ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip

2015 ◽  
Vol 23 (12) ◽  
pp. 3015-3028 ◽  
Author(s):  
Ioannis Seitanidis ◽  
Anastasios Psarras ◽  
Kypros Chrysanthou ◽  
Chrysostomos Nicopoulos ◽  
Giorgos Dimitrakopoulos
Keyword(s):  
Virtual Channel ◽  
Networks On Chip ◽  
On Chip

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip

scholarly journals Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications

2018 ◽  
Vol 8 (4) ◽  
pp. 39 ◽  
Author(s):  
Franco Fuschini ◽  
Marina Barbiroli ◽  
Marco Zoli ◽  
Gaetano Bellanca ◽  
Giovanna Calò ◽  
...  
Keyword(s):  
Ray Tracing ◽  
Path Loss ◽  
Wireless Channel ◽  
Electromagnetic Propagation ◽  
Networks On Chip ◽  
Spatial Properties ◽  
Radiation Properties ◽  
Wireless Optical Communications ◽  
On Chip ◽  
The Relationship

Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties.

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

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