Energy recovery design for low-power ASICs

2004 ◽  
Author(s):  
C.H. Ziesler ◽  
Joohee Kim ◽  
M.C. Papaefthymiou ◽  
Suhwan Kim
Keyword(s):  
Low Power ◽  
Energy Recovery ◽  
Recovery Design

Low power energy recovery clock

2014 ◽  
Author(s):  
Supreeth M.S. ◽  
D. Jennifer Judy ◽  
Kore Sagar ◽  
V.S. Kanchana Bhaaskaran
Keyword(s):  
Low Power ◽  
Energy Recovery

scholarly journals Low-Power Adiabatic Computing with Modified Quasi Static Energy Recovery Logic of MQSERL 4x4 multiplier

2019 ◽  
Vol 8 (2) ◽  
pp. 1896-1901
Keyword(s):  
Low Power ◽  
Energy Recovery ◽  
Test System ◽  
Flip Flop ◽  
Static Energy ◽  
Adiabatic Computing

This work depends on another methodology for limiting vitality utilization in semi static vitality recuperation rationale of Modified Quasi Static Energy Recovery Logic (MQSERL) circuit which includes enhancement by expelling the non-adiabatic misfortunes totally. Vitality recouping hardware dependent on adiabatic standards is a promising system driving towards low power superior circuit plan. The productivity of such circuits might be expanded by lessening the adiabatic and non-adiabatic misfortunes drawn by them amid the charging and recuperation tasks. In this paper, execution of the proposed rationale style is broke down and contrasted and CMOS in their agent inverters, entryways, flip- flop and snake circuits. Every one of the circuit was reproduced by test system of TANNER TOOL in 0.18μm innovation. In our proposed inverter the vitality proficiency has been enhanced to practically 30% and 20% up to 20MHz and 20fF outside load capacitance in contrast with CMOS and MQSERL circuits individually. Our proposed circuit gives vitality proficient execution up to 100 MHz and in this way it has ended up being utilized in superior VLSI hardware.

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