A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

2012 International SoC Design Conference (ISOCC) ◽

10.1109/isocc.2012.6407050 ◽

2012 ◽

Cited By ~ 1

Author(s):

Jinsoo Rhim ◽

Kwang-Chun Choi ◽

Woo-Young Choi

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Area Efficient

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A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2008.2008520 ◽

2009 ◽

Vol 56 (1) ◽

pp. 6-10 ◽

Cited By ~ 22

Author(s):

Young-Suk Seo ◽

Jang-Woo Lee ◽

Hong-Jung Kim ◽

Changsik Yoo ◽

Jae-Jin Lee ◽

...

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Phase Detector ◽

Linear Phase

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Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.385-386.1278 ◽

2013 ◽

Vol 385-386 ◽

pp. 1278-1281 ◽

Cited By ~ 1

Author(s):

Zheng Fei Hu ◽

Ying Mei Chen ◽

Shao Jia Xue

Keyword(s):

Optical Communication ◽

Input Data ◽

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Phase Detector ◽

Voltage Controlled Oscillator ◽

Output Data ◽

Data Phase ◽

Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

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Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit using deep-submicron digital CMOS technology

IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings. ◽

10.1109/soc.2003.1241471 ◽

2004 ◽

Cited By ~ 3

Author(s):

Z.O. Gursoy ◽

Y. Leblebici

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Deep Submicron ◽

Data Recovery ◽

Digital Cmos

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All-digital clock and data recovery circuit for USB applications in 65 nm CMOS technology

AEU - International Journal of Electronics and Communications ◽

10.1016/j.aeue.2019.02.020 ◽

2019 ◽

Vol 103 ◽

pp. 1-12 ◽

Cited By ~ 4

Author(s):

Sanaz Salem ◽

Mohsen Saneei

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Digital Clock

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A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2015.2409987 ◽

2016 ◽

Vol 24 (2) ◽

pp. 578-586 ◽

Cited By ~ 8

Author(s):

Shuai Chen ◽

Hao Li ◽

Patrick Yin Chiang

Keyword(s):

Clock And Data Recovery ◽

High Density ◽

Data Recovery ◽

Digital Clock ◽

28 Nm ◽

Area Efficient

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6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology

2017 IEEE International Solid-State Circuits Conference (ISSCC) ◽

10.1109/isscc.2017.7870286 ◽

2017 ◽

Cited By ~ 7

Author(s):

Jaeduk Han ◽

Yue Lu ◽

Nicholas Sutardja ◽

Elad Alon

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Adaptive Equalization ◽

Baud Rate

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A Clock and Data Recovery Circuit for the ALTAS/CMS HL-LHC Pixel Front End Chip in 65 nm CMOS Technology

10.22323/1.370.0046 ◽

2020 ◽

Author(s):

Konstantinos Moustakas ◽

P. Rymaszewski ◽

T. Hemperek ◽

H. Krüger ◽

M. Vogt ◽

...

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Front End

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A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2003.818566 ◽

2003 ◽

Vol 38 (12) ◽

pp. 2181-2190 ◽

Cited By ~ 98

Author(s):

Jri Lee ◽

B. Razavi

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery

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Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2017.2740268 ◽

2017 ◽

Vol 52 (12) ◽

pp. 3474-3485 ◽

Cited By ~ 13

Author(s):

Jaeduk Han ◽

Nicholas Sutardja ◽

Yue Lu ◽

Elad Alon

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Adaptive Equalization ◽

Baud Rate ◽

Design Techniques

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A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology

2012 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2012.6271836 ◽

2012 ◽

Cited By ~ 1

Author(s):

Bo-Qian Jiang ◽

Cheng-Liang Hung ◽

Bing-Hung Chen ◽

Kuo-Hsing Cheng

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery

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A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

Design and realization of a 2.4 Gbps - 3.2 Gbps clock and data recovery circuit using deep-submicron digital CMOS technology

All-digital clock and data recovery circuit for USB applications in 65 nm CMOS technology

A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology

A Clock and Data Recovery Circuit for the ALTAS/CMS HL-LHC Pixel Front End Chip in 65 nm CMOS Technology

A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology

Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology

A 6-Gb/s 3X-oversampling-like clock and data recovery in 0.13-µm CMOS technology

All-digital clock and data recovery circuit for USB applications in 65 nm CMOS technology