Shared-Cache Simulation for Multi-core System with LRU2-MRU Collaborative Cache Replacement Algorithm

2012 ◽  
Author(s):  
Shan Ding ◽  
Shiya Lui ◽  
Yuanyuan Li
Keyword(s):  
Cache Replacement ◽  
Core System ◽  
Shared Cache ◽  
Replacement Algorithm ◽  
Cache Simulation

An Aggregation Cache Replacement algorithm based on ontology clustering

2006 ◽  
Vol 11 (5) ◽  
pp. 1141-1146
Author(s):  
Zhu Jiang ◽  
Shen Qingguo ◽  
Tang Tang ◽  
Li Yongqiang
Keyword(s):  
Cache Replacement ◽  
Replacement Algorithm

scholarly journals Partially shared cache and adaptive replacement algorithm for NoC-based many-core systems

2019 ◽  
Vol 98 ◽  
pp. 424-433 ◽  
Author(s):  
Pengfei Yang ◽  
Quan Wang ◽  
Hongwei Ye ◽  
Zhiqiang Zhang
Keyword(s):  
Shared Cache ◽  
Replacement Algorithm ◽  
Many Core

IMPROVING peLIFO CACHE REPLACEMENT POLICY: HARDWARE REDUCTION AND THREAD-AWARE EXTENSION

2014 ◽  
Vol 23 (04) ◽  
pp. 1450046
Author(s):  
ENRIQUE SEDANO ◽  
SILVIO SEPULVEDA ◽  
FERNANDO CASTRO ◽  
DANIEL CHAVER ◽  
RODRIGO GONZALEZ-ALBERQUILLA ◽  
...  
Keyword(s):  
New York ◽  
Replacement Policy ◽  
Cache Replacement ◽  
Dynamic Information ◽  
Processor Performance ◽  
Replacement Algorithm ◽  
L2 Cache ◽  
Cache Efficiency ◽  
Performance Penalty

Studying blocks behavior during their lifetime in cache can provide useful information to reduce the miss rate and therefore improve processor performance. According to this rationale, the peLIFO replacement algorithm [M. Chaudhuri, Proc. Micro'09, New York, 12–16 December, 2009, pp. 401–412], which learns dynamically the number of cache ways required to satisfy short-term reuses preserving the remaining ways for long-term reuses, has been recently proposed. In this paper, we propose several changes to the original peLIFO policy in order to reduce the implementation complexity involved, and we extend the algorithm to a shared-cache environment considering dynamic information about threads behavior to improve cache efficiency. Experimental results confirm that our simplification techniques reduce the required hardware with a negligible performance penalty, while the best of our thread-aware extension proposals reduces average CPI by 8.7% and 15.2% on average compared to the original peLIFO and LRU respectively for a set of 43 multi-programmed workloads on an 8 MB 16-way set associative shared L2 cache.

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