A Reconfigurable Memory PUF Based on Tristate Inverter Arrays
Keyword(s):
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-/spl mu/m CMOS
2005 ◽
Vol 40
(1)
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pp. 261-275
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2011 ◽
Vol 57
(3)
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pp. 1345-1353
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Keyword(s):
2002 ◽
Vol 51
(6)
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pp. 1300-1311
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2020 ◽
Vol E103.D
(3)
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pp. 578-589
2008 ◽
Vol 47
(4)
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pp. 2774-2778
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