Mapping a multiple antenna SDM-OFDM receiver on the ADRES coarse-grained reconfigurable processor

2006 ◽  
Author(s):  
D. Novo ◽  
W. Moffat ◽  
V. Derudder ◽  
B. Bougard
Keyword(s):  
Coarse Grained ◽  
Multiple Antenna ◽  
Reconfigurable Processor

Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array

2015 ◽  
Vol 24 (03) ◽  
pp. 1550043 ◽  
Author(s):  
Chen Yang ◽  
Leibo Liu ◽  
Yansheng Wang ◽  
Shouyi Yin ◽  
Peng Cao ◽  
...  
Keyword(s):  
Input Data ◽  
Multimedia System ◽  
Coarse Grained ◽  
Reconfigurable Processor ◽  
Decoding Algorithms ◽  
High Profile ◽  
Context Switching ◽  
Reconfigurable Arrays ◽  
Reconfigurable Array ◽  
Major Bottleneck

The major bottleneck of coarse-grained reconfigurable arrays (CGRAs) is the excessive configuration overhead; as a result, computing potential cannot be fully utilized. At run-time, the function of CGRAs can be fully and dynamically reconfigured by changing contexts. Therefore, the frequency of context switching on CGRAs is very high. On the other hand, the configuration time of CGRAs is very long. This paper proposes three configuration approaches to reduce interval latency when switching configuration contexts. These proposed approaches include input data relocation (IDR), line-based context switching (LCS), and loop interval minimization (LIM). IDR relocates input data to the first stage of the pipeline; as a result, the delay time for the input data of the next data flow graph (DFG) is reduced. LCS is a LCS mechanism for adjacent independent DFGs to reduce the interval of context switching, thereby expanding the depth of the pipeline. LIM is used to minimize the interval of loops. Simulations on a coarse-grained reconfigurable processor called reconfigurable multimedia system (REMUS) show that 1080 p@30 fps for H.264 high profile video decoding can be achieved under 200 MHz working frequency. As for AVS and MPEG2 decoding algorithms, much higher performance, i.e., 1080 p@39 fps and 1080 p@41 fps, can be achieved respectively.

scholarly journals CHiPReP—A Compiler for the HiPReP High-Performance Reconfigurable Processor

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2590
Author(s):  
Markus Weinhardt ◽  
Mohamed Messelka ◽  
Philipp Käsgen
Keyword(s):  
High Performance ◽  
Optimization Method ◽  
Coarse Grained ◽  
Splitting Algorithm ◽  
Reconfigurable Processor ◽  
Routing Optimization ◽  
Integrated Placement ◽  
Reconfigurable Array ◽  
Address Generator ◽  
Scheduling Heuristic

This article presents CHiPReP, a C compiler for the HiPReP processor, which is a high-performance Coarse-Grained Reconfigurable Array employing Floating-Point Units. CHiPReP is an extension of the LLVM and CCF compiler frameworks. Its main contributions are (i) a Splitting Algorithm for Data Dependence Graphs, which distributes the computations of a C loop to Address-Generator Units and Processing Elements; (ii) a novel instruction clustering and scheduling heuristic; and (iii) an integrated placement, pipeline balancing and routing optimization method based on Simulated Annealing. The compiler was verified and analyzed using a cycle-accurate HiPReP simulation model.

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