Exploiting component/event-level parallelism in concurrent fault and design error simulation

2002 ◽  
Author(s):  
S.A. Shaikh ◽  
S.A. Szygenda
Keyword(s):  
Design Error ◽  
Component Event ◽  
Level Parallelism ◽  
Error Simulation

Diagnose Compound Hold Time Faults Caused by Spot Delay Defects at Clock Tree

2011 ◽  
Author(s):  
Yu Huang ◽  
Wu-Tung Cheng ◽  
Ting-Pu Tai ◽  
Liyang Lai ◽  
Ruifeng Guo ◽  
...  
Keyword(s):  
Hold Time ◽  
Clock Signal ◽  
Clock Tree ◽  
Scan Testing ◽  
Design Error ◽  
Functional Logic ◽  
Scan Chains ◽  
Delay Defects

Abstract If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. It makes the diagnosis of such defect especially difficult if the defective clock signal is used for both shift and capture operations during the scan testing, because (1) the defect induces hold time faults on scan chains during shift cycles, and (2) hold-time faults may also be introduced during capture cycles in the functional logic paths. In this paper we illustrate the failure behaviors of such clock defects and propose an algorithm to diagnose it.

The representation of the analysis effect in three error simulation techniques

2006 ◽  
Author(s):  
Loïk Berre ◽  
Simona Ecaterina Åžtefănescu ◽  
Margarida Belo Pereira
Keyword(s):  
Simulation Techniques ◽  
Error Simulation
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