scholarly journals Smart cache: A self adaptive cache architecture for energy efficiency

Author(s):  
Karthik T. Sundararajan ◽  
Timothy M. Jones ◽  
Nigel Topham
2019 ◽  
Vol 75 (11) ◽  
pp. 7076-7100 ◽  
Author(s):  
Wenxia Guo ◽  
Ping Kuang ◽  
Yaqiu Jiang ◽  
Xiang Xu ◽  
Wenhong Tian

2003 ◽  
Vol 2 (2) ◽  
pp. 163-185 ◽  
Author(s):  
Soontae Kim ◽  
N. Vijaykrishnan ◽  
Mahmut Kandemir ◽  
Anand Sivasubramaniam ◽  
Mary Jane Irwin

Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Jouni Isoaho ◽  
Hannu Tenhunen

The self-adaptive Network-on-Chip (NoC) is a promising communication architecture for massively parallel embedded systems. With constant technology scaling and the consequent stronger influence of process variations, the necessity of run-time monitoring and adaptive reconfiguration becomes widely acknowledged. This article presents a survey of existing techniques and methods, in particular for energy efficiency and dependability. The article firstly examines the motivation of self-adaptive computing in parallel embedded systems. A self-adaptive system model is abstracted, which is composed of goals, monitoring interface, and self-adaptation. Based on the model, the authors extensively survey previous works addressing adaptive NoCs with different monitoring techniques and reconfiguration methods, for power/energy optimization and dependability enhancement. Several design examples are elaborated which serve proper guiding purposes. The authors also identify important issues which are often overlooked or deserve more attention. The article provides review and insight for future design on this topic.


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