Survey of Self-Adaptive NoCs with Energy-Efficiency and Dependability

2012 ◽  
Vol 3 (2) ◽  
pp. 1-22 ◽  
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Jouni Isoaho ◽  
Hannu Tenhunen
Keyword(s):  
Energy Efficiency ◽  
Embedded Systems ◽  
Adaptive System ◽  
Process Variations ◽  
Communication Architecture ◽  
Technology Scaling ◽  
Future Design ◽  
Self Adaptation ◽  
On Chip ◽  
Self Adaptive

The self-adaptive Network-on-Chip (NoC) is a promising communication architecture for massively parallel embedded systems. With constant technology scaling and the consequent stronger influence of process variations, the necessity of run-time monitoring and adaptive reconfiguration becomes widely acknowledged. This article presents a survey of existing techniques and methods, in particular for energy efficiency and dependability. The article firstly examines the motivation of self-adaptive computing in parallel embedded systems. A self-adaptive system model is abstracted, which is composed of goals, monitoring interface, and self-adaptation. Based on the model, the authors extensively survey previous works addressing adaptive NoCs with different monitoring techniques and reconfiguration methods, for power/energy optimization and dependability enhancement. Several design examples are elaborated which serve proper guiding purposes. The authors also identify important issues which are often overlooked or deserve more attention. The article provides review and insight for future design on this topic.

Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

2010 ◽  
Vol 18 (4) ◽  
pp. 527-540 ◽  
Author(s):  
Teijo Lehtonen ◽  
David Wolpert ◽  
Pasi Liljeberg ◽  
Juha Plosila ◽  
Paul Ampadu
Keyword(s):  
Adaptive System ◽  
On Chip ◽  
Self Adaptive

Self-Adaptive SoCs for Dependability

2014 ◽  
pp. 1-21
Author(s):  
Liang Guang ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
Large Scale ◽  
Future Research ◽  
Great Promise ◽  
Primary Concern ◽  
Technology Scaling ◽  
Computing Paradigm ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Self Adaptive

Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI) chips. Centralized, distributed, and hierarchical fault management, utilizing various redundancy schemes and exploiting logical or physical reconfiguration methods, are all examined. As future research directions, the challenge of integrating different error management schemes to account for multifold threats and the great promise of error resilient computing are identified. This chapter provides, for chip designers, much needed insights on applying a self-adaptive computing paradigm to approach dependability on error-prone, cost-sensitive SoCs.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals An Automatic Offset Calibration Method for Differential Charge-Based Capacitance Measurement

2021 ◽  
Vol 11 (2) ◽  
pp. 22
Author(s):  
Umberto Ferlito ◽  
Alfio Dario Grasso ◽  
Michele Vaiana ◽  
Giuseppe Bruno
Keyword(s):  
Standard Deviation ◽  
Output Voltage ◽  
Process Variations ◽  
Calibration Method ◽  
Capacitance Measurement ◽  
Effective Technique ◽  
Fully Integrated ◽  
Front End ◽  
Novel Method ◽  
On Chip

Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.

High-Speed On-Chip Event Counters for Embedded Systems

2009 ◽  
Author(s):  
Nilanjan Mukherjee ◽  
Artur Pogiel ◽  
Janusz Rajski ◽  
Jerzy Tyszer
Keyword(s):  
Embedded Systems ◽  
High Speed ◽  
On Chip
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