Wear-leveling for PCM main memory on embedded system via page management and process scheduling

2014 ◽  
Author(s):  
Chen Pan ◽  
Mimi Xie ◽  
Jingtong Hu ◽  
Meikang Qiu ◽  
Qingfeng Zhuge
Keyword(s):  
Embedded System ◽  
Main Memory ◽  
Process Scheduling ◽  
Wear Leveling

Study of Embedded Operating System Process Scheduling

2013 ◽  
Vol 347-350 ◽  
pp. 1598-1601
Author(s):  
Jin Hai Zhang
Keyword(s):  
Operating System ◽  
Embedded System ◽  
Hot Spots ◽  
Scheduling Algorithm ◽  
Embedded Operating System ◽  
System Software ◽  
Information Industry ◽  
Process Scheduling ◽  
The Core ◽  
Industry Research

Embedded systems are widely used in industries, its amazing to develop speed and as an embedded system software for embedded operating system is at the core of the information industry research hot spots. This thesis is mainly embedded in different application environments, the operating system discussion and research on how to implement its process scheduling algorithm.

Wear-Leveling Aware Page Management for Non-Volatile Main Memory on Embedded Systems

2016 ◽  
Vol 2 (2) ◽  
pp. 129-142 ◽  
Author(s):  
Chen Pan ◽  
Shouzhen Gu ◽  
Mimi Xie ◽  
Yongpan Liu ◽  
Chun Jason Xue ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Main Memory ◽  
Wear Leveling

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

2009 ◽  
Author(s):  
Moinuddin K. Qureshi ◽  
John Karidis ◽  
Michele Franceschini ◽  
Vijayalakshmi Srinivasan ◽  
Luis Lastras ◽  
...  
Keyword(s):  
Main Memory ◽  
Wear Leveling

Tnvmalloc: A Thread-Level-Based Wear-Aware Allocator for Nonvolatile Main Memory

2021 ◽  
Author(s):  
Chunhua Xiao ◽  
Lin Zhang ◽  
Mingliang Zhou
Keyword(s):  
Data Structure ◽  
Open Problem ◽  
Memory Management ◽  
Main Memory ◽  
Wear Leveling ◽  
Large Memory

The nonvolatile main memory (NVMM) has the advantages of near-DRAM speed, byte-addressability, and persistence, and presents limitations in write durability. The memory allocator, a fundamental data structure of memory management, can effectively mitigate the wear speed, thereby prolonging the NVMM lifetime. Nevertheless, balancing the performance and writing reliability in single and multi-thread scenarios is still an open problem for NVMM allocators. In this paper, we propose a thread-level wear-aware allocator (Tnvmalloc) that divides the NVMM space into multiple management granularities and then dynamically selects the optimal blocks using a wear-leveling strategy based on allocation requests and wear records. Experiments show that the proposed Tnvmalloc provides more than 10 times improvement in wear-leveling than typical allocators Glibc malloc, NVMalloc, and nvm_malloc, which becomes obvious especially in multi-threaded scenarios. Moreover, when allocating large memory blocks, Tnvmalloc achieves three times faster than that of NVMalloc.

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