Bit error rate in NAND Flash memories

2008 ◽  
Author(s):  
Neal Mielke ◽  
Todd Marquart ◽  
Ning Wu ◽  
Jeff Kessenich ◽  
Hanmant Belgal ◽  
...  
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Nand Flash ◽  
Flash Memories

On Die Bit Error Rate Estimator for NAND Flash Memory

2017 ◽  
Vol 64 (7) ◽  
pp. 772-776 ◽  
Author(s):  
Mustafa N. Kaynak ◽  
Patrick R. Khayat ◽  
Sivagnanam Parthasarathy
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory

scholarly journals A Low-Cost Improved Method of Raw Bit Error Rate Estimation for NAND Flash Memory of High Storage Density

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1900
Author(s):  
Kainan Ma ◽  
Ming Liu ◽  
Tao Li ◽  
Yibo Yin ◽  
Hongda Chen
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Flash Memory ◽  
Low Cost ◽  
Estimation Method ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Storage Density ◽  
Raw Bit Error Rate ◽  
High Storage

Cells wear fast in NAND flash memory of high storage density (HSD), so it is very necessary to have a long-term frequent in-time monitoring on its raw bit error rate (RBER) changes through a fast RBER estimation method. As the flash of HSD already has relatively lower reading speed, the method should not further degrade its read performance. This paper proposes an improved estimation method utilizing known data comparison, includes interleaving to balance the uneven error distribution in the flash of HSD, a fast RBER estimation module to make the estimated RBER highly linearly correlated with the actual RBER, and enhancement strategies to accelerate the decoding convergence of low-density parity-check (LDPC) codes and thereby make up the rate penalty caused by the known data. Experimental results show that when RBER is close to the upper bound of LDPC code, the reading efficiency can be increased by 35.8% compared to the case of no rate penalty. The proposed method only occupies 0.039mm2 at 40nm process condition. Hence, the fast, read-performance-improving, and low-cost method is of great application potential on RBER monitoring in the flash of HSD.

scholarly journals Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with selective refresh

2019 ◽  
Vol 96 ◽  
pp. 37-45
Author(s):  
Emna Farjallah ◽  
Jean-Marc Armani ◽  
Valentin Gherman ◽  
Luigi Dilillo
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Nand Flash ◽  
Raw Bit Error Rate

scholarly journals Bit-error rate improvement of TLC NAND Flash using state re-ordering

2012 ◽  
Vol 9 (23) ◽  
pp. 1775-1779 ◽  
Author(s):  
Ik Joon Chang ◽  
Joon-Sung Yang
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Nand Flash ◽  
Rate Improvement
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