Networking Challenges in High-Capacity, Low-Latency, Optically-Switched Interconnects

Author(s):  
M. Dales ◽  
M. Glick
Keyword(s):  
Author(s):  
Kiyo Ishii ◽  
Junya Kurumida ◽  
Atsuko Takefusa ◽  
Takayuki Kurosu ◽  
Tomohiro Kudoh ◽  
...  

Energies ◽  
2019 ◽  
Vol 12 (18) ◽  
pp. 3449 ◽  
Author(s):  
Kelechi ◽  
Alsharif ◽  
Ramly ◽  
Abdullah ◽  
Nordin

Network latency will be a critical performance metric for the Fifth Generation (5G) networks expected to be fully rolled out in 2020 through the IMT-2020 project. The multi-user multiple-input multiple-output (MU-MIMO) technology is a key enabler for the 5G massive connectivity criterion, especially from the massive densification perspective. Naturally, it appears that 5G MU-MIMO will face a daunting task to achieve an end-to-end 1 ms ultra-low latency budget if traditional network set-ups criteria are strictly adhered to. Moreover, 5G latency will have added dimensions of scalability and flexibility compared to prior existing deployed technologies. The scalability dimension caters for meeting rapid demand as new applications evolve. While flexibility complements the scalability dimension by investigating novel non-stacked protocol architecture. The goal of this review paper is to deploy ultra-low latency reduction framework for 5G communications considering flexibility and scalability. The Four (4) C framework consisting of cost, complexity, cross-layer and computing is hereby analyzed and discussed. The Four (4) C framework discusses several emerging new technologies of software defined network (SDN), network function virtualization (NFV) and fog networking. This review paper will contribute significantly towards the future implementation of flexible and high capacity ultra-low latency 5G communications.


2021 ◽  
Author(s):  
Jean Paul Linnartz ◽  
Carina Ribeiro Barbio Corrêa ◽  
Thiago Elias Bitencourt Cunha ◽  
Eduward Tangdiongga ◽  
Ton Koonen ◽  
...  

Abstract Communication for the Internet of Things (IoT) currently is predominantly narrowband and cannot always guarantee low latency and high reliability. Future IoT applications such as flexible manufacturing, augmented reality and self-driving vehicles rely on sophisticated real-time processing in the cloud to which mobile IoT devices are connected. High-capacity links that meet the requirements of the upcoming 6G systems cannot easily be provided by the current radio-based communication infrastructure. Light communication, which is also denoted as LiFi, offers huge amounts of spectrum, extra security and low-latency transmission free of interference even in dense reuse settings. We present the current state-of-the-art of LiFi systems and introduce new features needed for future IoT applications. We discuss results from a distributed multiple-input multiple-output topology with a fronthaul using plastic optical fiber. We evaluate seamless mobility between the light access points and also handovers to 5G, besides low power transmission and integrated positioning. Future LiFi development, implementation and efforts towards standardization are addressed in the EU ELIoT project which is presented here.


Micromachines ◽  
2019 ◽  
Vol 10 (2) ◽  
pp. 124 ◽  
Author(s):  
Ho Shin ◽  
Eui-Young Chung

Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2D-DRAMs. Although there are various cache management techniques and latency hiding schemes to reduce DRAM access time, in a high-performance system using high-capacity 3D-stacked DRAM, it is ultimately essential to reduce the latency of the DRAM itself. To solve this problem, various asymmetric in-DRAM cache structures have recently been proposed, which are more attractive for high-capacity DRAMs because they can be implemented at a lower cost in 3D-stacked DRAMs. However, most research mainly focuses on the architecture of the in-DRAM cache itself and does not pay much attention to proper management methods. In this paper, we propose two new management algorithms for the in-DRAM caches to achieve a low-latency and low-power 3D-stacked DRAM device. Through the computing system simulation, we demonstrate the improvement of energy delay product up to 67%.


Author(s):  
John S. Vardakas ◽  
Idelfonso Tafur Monroy ◽  
Lena Wosinska ◽  
George Agapiou ◽  
Romain Brenot ◽  
...  
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