Wire-routing machines—New tools for VLSI physical design

In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

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ON FINDING A STAIRCASE CHANNEL WITH MINIMUM CROSSING NETS IN A VLSI FLOORPLAN

Journal of Circuits System and Computers ◽

10.1142/s0218126604001854 ◽

2004 ◽

Vol 13 (05) ◽

pp. 1019-1038 ◽

Cited By ~ 4

Author(s):

SUBHASHIS MAJUMDER ◽

SUBHAS C. NANDY ◽

BHARGAB B. BHATTACHARYA

Keyword(s):

Network Flow ◽

Time Algorithm ◽

Deep Submicron ◽

Vlsi Chip ◽

Polynomial Time Algorithms ◽

Wire Routing ◽

Vlsi Physical Design ◽

Polygonal Region ◽

Block Placement ◽

Circuit Blocks

A VLSI chip is fabricated by integrating several rectangular circuit blocks on a 2D silicon floor. The circuit blocks are assumed to be placed isothetically and the netlist attached to each block is given. For wire routing, the terminals belonging to the same net are to be electrically interconnected using conducting paths. A staircase channel is an empty polygonal region on the silicon floor bounded by two monotonically increasing (or decreasing) staircase paths from one corner of the floor to its diagonally opposite corner. The staircase paths are defined by the boundaries of the blocks. In this paper, the problem of determining a monotone staircase channel on the floorplan is considered such that the number of distinct nets whose terminals lie on both sides of the channel, is minimized. Two polynomial-time algorithms are presented based on the network flow paradigm. First, the simple two-terminal net model is considered, i.e., each net is assumed to connect exactly two blocks, for which an O(n×k) time algorithm is proposed, where n and k are respectively the number of blocks and nets on the floor. Next, the algorithm is extended to the more realistic case of multi-terminal net problem. The time complexity of the latter algorithm is O((n+k)×T), where T is the total number of terminals attached to all nets in the floorplan. Solutions to these problems are useful in modeling the repeater block placement that arises in interconnect-driven floorplanning for deep-submicron VLSI physical design. It is also an important problem in context to the classical global routing, where channels are used as routing space on silicon.

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Using XML for VLSI Physical Design Automation

Algorithms and Architectures for Parallel Processing - Lecture Notes in Computer Science ◽

10.1007/978-3-642-03095-6_77 ◽

2009 ◽

pp. 821-831

Author(s):

Fong-Ming Shyu ◽

Po-Hsun Cheng ◽

Sao-Jie Chen

Keyword(s):

Design Automation ◽

Physical Design ◽

Vlsi Physical Design

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