Wirelength Based Clustering Technique for VLSI Physical Design

2007 ◽  
Author(s):  
Jie Huang ◽  
Jianhua Li ◽  
Logan Rakai ◽  
Laleh Behjat
Keyword(s):  
Physical Design ◽  
Clustering Technique ◽  
Vlsi Physical Design

VLSI physical design analyzer: A profiling and data mining tool

2015 ◽  
Author(s):  
Shikha Somani ◽  
Piyush Verma ◽  
Sriram Madhavan ◽  
Fadi Batarseh ◽  
Robert C. Pack ◽  
...  
Keyword(s):  
Data Mining ◽  
Physical Design ◽  
Data Mining Tool ◽  
Vlsi Physical Design ◽  
Mining Tool

scholarly journals Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

2014 ◽  
Vol 2014 ◽  
pp. 1-15 ◽  
Author(s):  
I. Hameem Shanavas ◽  
R. K. Gnanamurthy
Keyword(s):  
Genetic Algorithm ◽  
Evolutionary Algorithm ◽  
Design Automation ◽  
Large Scale ◽  
Hybrid Approach ◽  
Hybrid Genetic Algorithm ◽  
Optimal Solution ◽  
Physical Design ◽  
Silicon Area ◽  
Vlsi Physical Design

In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

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