A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature

2006 ◽  
Author(s):  
Kotaro Shimamura ◽  
Takeshi Takehara ◽  
Yosuke Shima ◽  
Kunihiko Tsunedomi
Keyword(s):  
Single Chip ◽  
Data Comparison ◽  
Fail Safe ◽  
With Memory

B303 DEVELOPMENT OF THE FAIL-SAFE SINGLE CHIP RISC-CPU BOARD

2003 ◽  
Vol 2003 (0) ◽  
pp. 271-275
Author(s):  
Toshihiko Kajiwara ◽  
Sei Takahashi ◽  
Munehisa Taira ◽  
Hidetaka Saegusa ◽  
Hideo Nakamura
Keyword(s):  
Single Chip ◽  
Fail Safe

Capito-Lunate Fusion with Memory Staples

2015 ◽  
Vol 04 (S 01) ◽  
Author(s):  
M. Solomons
Keyword(s):  
With Memory

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

Design of Predistorter with Efficient Updating Algorithm of Power Amplifier with Memory Effect

2012 ◽  
Vol E95-C (3) ◽  
pp. 382-394
Author(s):  
Yasuyuki OISHI ◽  
Shigekazu KIMURA ◽  
Eisuke FUKUDA ◽  
Takeshi TAKANO ◽  
Daisuke TAKAGO ◽  
...  
Keyword(s):  
Memory Effect ◽  
Power Amplifier ◽  
With Memory

Double Fail-Safe Attitude Control System for Artificial Meteor Microsatellite ALE-1

2021 ◽  
Vol 19 (1) ◽  
pp. 9-16
Author(s):  
Shinya FUJITA ◽  
Yuji SATO ◽  
Toshinori KUWAHARA ◽  
Yuji SAKAMOTO ◽  
Yoshihiko SHIBUYA ◽  
...  
Keyword(s):  
Control System ◽  
Attitude Control ◽  
Attitude Control System ◽  
Fail Safe
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