Power and Performance Efficient Partial Circuits in Packet-Switched Networks-on-Chip

2013 ◽  
Author(s):  
N. Teimouri ◽  
M. Modarressi ◽  
H. Sarbazi-Azad
Keyword(s):  
Networks On Chip ◽  
Switched Networks ◽  
And Performance ◽  
On Chip

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

Integration ◽  
2015 ◽  
Vol 50 ◽  
pp. 193-204
Author(s):  
Mehdi Modarressi ◽  
Nasibeh Teimouri ◽  
Hamid Sarbazi-azad
Keyword(s):  
Networks On Chip ◽  
Switched Networks ◽  
On Chip

High-Level Programming of Dynamically Reconfigurable NoC-Based Heterogeneous Multicore SoCs

2010 ◽  
pp. 186-219
Author(s):  
Wim Vanderbauwhede
Keyword(s):  
Cmos Technology ◽  
Design Reuse ◽  
Full Potential ◽  
Networks On Chip ◽  
Heterogeneous Multicore ◽  
Dynamically Reconfigurable ◽  
Ip Cores ◽  
And Performance ◽  
On Chip ◽  
High Level

With the increase in System-on-Chip (SoC) complexity and CMOS technology capabilities, the SoC design community has recently observed a convergence of a number of critical trends, all of them aimed at addressing the design gap: the advent of heterogeneous multicore SoCs and Networks-on-Chip and the recognition of the need for design reuse through Intellectual Property (IP) cores, for dynamic reconfigurability and for high abstraction-level design. In this chapter, we present a solution for High-level Programming of Dynamically Reconfigurable NoC-based Heterogeneous Multicore SoCs. Our solution, the Gannet framework, allows IP core-based Heterogeneous Multicore SoCs to be programmed using a high-level language whilst preserving the full potential for parallelism and dynamic reconfigurability inherent in such a system. The required hardware infrastructure is small and low-latency, thus adding full dynamic reconfiguration capabilities with a small overhead both in area and performance.

scholarly journals Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip

2018 ◽  
Vol 89 ◽  
pp. 103-117 ◽  
Author(s):  
Michael Opoku Agyeman ◽  
Ali Ahmadinia ◽  
Nader Bagherzadeh
Keyword(s):  
Networks On Chip ◽  
Application Mapping ◽  
And Performance ◽  
On Chip ◽  
3D Networks

Adaptive Networks for On-Chip Communication

2019 ◽  
pp. 655-666
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Quality Of Service ◽  
Network Topology ◽  
Second Generation ◽  
Network Interface ◽  
Adaptive Networks ◽  
Networks On Chip ◽  
Adaptive Processes ◽  
And Performance ◽  
On Chip

The second generation of network-on-chips (NoC) are dynamic or adaptive providing a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance, and quality of service compared to the previous generation where the architecture is decided at design time. To improve resource efficiency and performance, the NoC must consider adaptive processes at several architectural levels, including the routing protocols, the router, the network interface, and the network topology. This chapter focuses on adaptive networks-on-chip, namely adaptive topologies and adaptive routers.

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