Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express

2005 ◽  
Author(s):  
C. Sauer ◽  
M. Gries ◽  
J.I. Gomez ◽  
S. Weber ◽  
K. Keutzer
Keyword(s):  
Pci Express

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

PCI Express-Based NVMe Solid State Disk

2013 ◽  
Vol 464 ◽  
pp. 365-368 ◽  
Author(s):  
Ji Jun Hung ◽  
Kai Bu ◽  
Zhao Lin Sun ◽  
Jie Tao Diao ◽  
Jian Bin Liu
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Detailed Design ◽  
Pci Express ◽  
Storage Media ◽  
Solid State Disk ◽  
Memory Card ◽  
Non Volatile Memory ◽  
Flash Translation Layer

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

Design of Data Transfer System Based on PCI Express Interface Applied in High-Speed Railway

2012 ◽  
Vol 229-231 ◽  
pp. 1543-1546
Author(s):  
Xiao Bo Zhou ◽  
Min Xia ◽  
Hai Long Cheng
Keyword(s):  
Data Acquisition ◽  
Data Transmission ◽  
High Speed ◽  
Data Transfer ◽  
Transmission Method ◽  
High Speed Railway ◽  
Pci Express ◽  
Data Acquisition Card ◽  
High Speed Data Acquisition ◽  
High Speed Data

To improve data transmission performance of the data acquisition card, a design of high-speed data transmission system is proposed in the thesis. Using FPGA of programmable logic devices, adopting Verilog HDL of hardware description language, the design of modularization and DMA transmission method is implemented in FPGA. Eventually the design implements the data transmission with high-speed through PCI Express interface. Through simulation and verification based on hardware system, this design is proved to be feasible and can satisfy the performance requirements of data transmission in the high-speed data acquisition card applied in high-speed railway communication. The design also has some value of application and reference for a universal data acquisition card.

Transmitter and Receiver Equalizers Optimization for PCI Express Gen6.0 based on PAM4

2021 ◽  
Author(s):  
Roberto J. Ruiz-Urbina ◽  
Francisco E. Rangel-Patino ◽  
Jose E. Rayas-Sanchez ◽  
Edgar A. Vega-Ochoa ◽  
Omar H. Longoria-Gandara
Keyword(s):  
Pci Express
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