Single-chip multiprocessors: the rebirth of parallel processing

Author(s):  
G. Sohi
Author(s):  
Toru Kisuki ◽  
Masaki Wakabayashi ◽  
Junji Yamamoto ◽  
Keisuke Inoue ◽  
Hideharu Amano

2009 ◽  
Vol 2009 ◽  
pp. 1-14 ◽  
Author(s):  
Xinyu Li ◽  
Omar Hammami

Embedded system design is increasingly based on single chip multiprocessors because of the high performance and flexibility requirements. Embedded multiprocessors on FPGA provide the additional flexibility by allowing customization through addition of hardware accelerators on FPGA when parallel software implementation does not provide the expected performance. And the overall multiprocessor architecture is still kept for additional applications. This provides a transition to software only parallel implementation while avoiding pure hardware implementation. An automatic design flow is proposed well suited for data flow signal processing exhibiting both pipelining and data parallel mode of execution. Fork-Join model-based software parallelization is explored to find out the best parallelization configuration. C-based synthesis coprocessor is added to improve performance with more hardware resource usage. The Triple Data Encryption Standard (TDES) cryptographic algorithm on a 48-PE single-chip distributed memory multiprocessor is selected as an application example of the flow.


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