Design of speed, energy and power efficient reversible logic based vedic ALU for digital processors

2012 ◽  
Author(s):  
Abhishek Gupta ◽  
Utsav Malviya ◽  
Vinod Kapse
Keyword(s):  
Reversible Logic ◽  
Power Efficient

Design of a Power Efficient ALU Using Reversible Logic Gates

2018 ◽  
pp. 469-479
Author(s):  
B. Abdul Rahim ◽  
B. Dhananjaya ◽  
S. Fahimuddin ◽  
N. Bala Dastagiri
Keyword(s):  
Logic Gates ◽  
Reversible Logic ◽  
Power Efficient ◽  
Reversible Logic Gates

scholarly journals A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies

2013 ◽  
Vol 73 (14) ◽  
pp. 8-14
Author(s):  
Satish Sharma ◽  
Shyam Babu Singh ◽  
Shyam Akashe
Keyword(s):  
Reversible Logic ◽  
Power Efficient

scholarly journals High functionality reversible arithmetic logic unit

2020 ◽  
Vol 10 (3) ◽  
pp. 2329
Author(s):  
Shaveta Thakral ◽  
Dipali Bansal
Keyword(s):  
Power Dissipation ◽  
Logic Gates ◽  
Reversible Logic ◽  
Logic Design ◽  
Quantum Cost ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Reversible Logic Gates ◽  
Reversible Alu ◽  
Logic Unit

Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.

scholarly journals Power Efficient Arithmetic Logic Unit Design using Reversible Logic

2015 ◽  
Vol 128 (6) ◽  
pp. 36-41
Author(s):  
Naman Sharma ◽  
Rajat Sachdeva ◽  
Upanshu Saraswat ◽  
Rajat Yadav ◽  
Gunjeet Kaur
Keyword(s):  
Reversible Logic ◽  
Power Efficient ◽  
Arithmetic Logic Unit ◽  
Unit Design ◽  
Logic Unit
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