Modeling System-Level Power Consumption Profiles Using RAPL

2018 ◽  
Author(s):  
James Phung ◽  
Young Choon Lee ◽  
Albert Y. Zomaya
Keyword(s):  
Power Consumption ◽  
System Level

A Wideband Continuous Time Quadrature Delta Sigma Modulator Based on a Real DSM for Low Power WLAN Receiver

2017 ◽  
Vol 27 (03) ◽  
pp. 1850044 ◽  
Author(s):  
Alireza Shamsi ◽  
Esmaeil Najafi Aghdam
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Time ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Complex Coefficient ◽  
Loop Filter ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Excess Loop Delay

Power consumption and bandwidth are two of the most important parameters in design of low power wideband modulators as power consumption is growing with the increase in bandwidth. In this study, a multi bit wideband low-power continuous time feed forward quadrature delta sigma modulator (CT-FF-QDSM) is designed for WLAN receiver applications by eliminating adders from modulator structure. In this method, a real modulator is designed and its excess loop delay (ELD) is compensated, then, it is converted into a quadrature structure by applying the complex coefficient to loop filter. Complex coefficients are extracted by the aid of a genetic algorithm to further improve signal to noise ratio (SNR) for bandwidth. One of the disadvantages of CT-FF-QDSM is the adders of loop filters which are power hungry and reduce the effective loop gain. Therefore, the adders have been eliminated while the transfer function is intact in the final modulator. The system level SNR of the proposed modulator is 62.53[Formula: see text]dB using OSR of 12. The circuit is implemented in CMOSTSMC180nm technology. The circuit levels SNR and power consumption are 54[Formula: see text]dB and 13.5[Formula: see text]mW, respectively. Figure of Merit (FOM) obtained from the proposed modulator is about 0.824 (pj/conv) which is improved (by more than 40%) compared to the previous designs.

Application of DFG Model on SOPC Technology

2012 ◽  
Vol 198-199 ◽  
pp. 696-700
Author(s):  
Wen Liang Niu ◽  
Wen Zheng Li ◽  
Kai Shuang Yin
Keyword(s):  
Power Consumption ◽  
Data Flow ◽  
Design Method ◽  
Digital Signal ◽  
Instrument Design ◽  
System Level ◽  
Digital Instrument ◽  
Signal Process ◽  
Digital Signal Process ◽  
Graphic Model

HW/SW (hardware/software) co-design method based on analysis and optimization of DFG (data flow graphic) model is introduced for SOPC (System on a Programmable Chip) used for digital instrument design in this paper. The method is based on the DFG model of the digital signal process algorithm and implemented with SOPC technology. The DFG model could help designer to divide the function into hardware and software respectively, therefore, the optimizing analysis at system level and circuit level of a SOPC used for portable logic analyzer shows that the DFG model is very useful for not only optimizing architecture and power consumption, but also HW/SW co-design.

scholarly journals Subthreshold Region based Linear Feedback Shift Register

2019 ◽  
Vol 8 (6S2) ◽  
pp. 817-821
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
System Level ◽  
Linear Feedback ◽  
Portable Devices ◽  
Subthreshold Region ◽  
Flip Flop ◽  
Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

scholarly journals Power Efficient, Low Noise 2-5 GHz Phase Locked Loop

2011 ◽  
Vol 16 (4) ◽  
pp. 66-72
Author(s):  
V.Sh. Melikyan ◽  
A.A. Durgaryan ◽  
H.P. Petrosyan ◽  
A.G. Stepanyan
Keyword(s):  
Power Consumption ◽  
Efficient Solution ◽  
Phase Locked Loop ◽  
Low Noise ◽  
System Level ◽  
Voltage Controlled Oscillator ◽  
Power Efficient ◽  
Area Overhead ◽  
Output Noise ◽  
5 Ghz

A power and noise efficient solution for phase locked loop (PLL) is presented. A lock detector is implemented to deactivate the PLL components, except the voltage controlled oscillator (VCO), in the locked state. Signals deactivating/activating the PLL are discussed on system level. The introduced technique significantly saves power and decreases PLL output jitter. As a result whole PLL power consumption and output noise decreased about 35-38% in expense of approximately 17% area overhead

scholarly journals Characterizing System-Level Masking Effects against Soft Errors

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2286
Author(s):  
Yohan Ko
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
System Reliability ◽  
Soft Errors ◽  
System Level ◽  
Register File ◽  
System Failures ◽  
Early Design ◽  
Lifetime Analysis ◽  
Estimate Reliability

From early design phases to final release, the reliability of modern embedded systems against soft errors should be carefully considered. Several schemes have been proposed to protect embedded systems against soft errors, but they are neither always functional nor robust, even with expensive overhead in terms of hardware area, performance, and power consumption. Thus, system designers need to estimate reliability quantitatively to apply appropriate protection techniques for resource-constrained embedded systems. Vulnerability modeling based on lifetime analysis is one of the most efficient ways to quantify system reliability against soft errors. However, lifetime analysis can be inaccurate, mainly because it fails to comprehensively capture several system-level masking effects. This study analyzes and characterizes microarchitecture-level and software-level masking effects by developing an automated framework with exhaustive fault injections (i.e., soft errors) based on a cycle-accurate gem5 simulator. We injected faults into a register file because errors in the register file can easily be propagated to other components in a processor. We found that only 5% of injected faults can cause system failures on an average over benchmarks, mainly from the MiBench suite. Further analyses showed that 71% of soft errors are overwritten by write operations before being used, and the CPU does not use 20% of soft errors at all after fault injections. The remainder are also masked by several software-level masking effects, such as dynamically dead instructions, compare and logical instructions that do not change the result, and incorrect control flows that do not affect program outputs.

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