Dynamic Exerciser Template Weighting in x86 Processor Verification

2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV) ◽

10.1109/mtv.2017.19 ◽

2017 ◽

Author(s):

Ahmed Wahba ◽

Justin Hohnerlein ◽

Farhan Rahman ◽

Li-C. Wang

Keyword(s):

Processor Verification

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Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification

10.21236/ada346065 ◽

1998 ◽

Cited By ~ 4

Author(s):

Sergey Berezin ◽

Armin Biere ◽

Edmund Clarke ◽

Yunshan Zhu

Keyword(s):

Model Checking ◽

Symbolic Model Checking ◽

Symbolic Model ◽

Processor Verification

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Background on Processor Verification

Symbolic Simulation Methods for Industrial Formal Verification ◽

10.1007/978-1-4615-1101-4_6 ◽

2002 ◽

pp. 97-104

Author(s):

Robert B. Jones

Keyword(s):

Processor Verification

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Processor Verification

Customizable Embedded Processors ◽

10.1016/b978-012369526-0/50013-9 ◽

2007 ◽

pp. 281-302

Author(s):

Daniel Große ◽

Rolf Drechsler ◽

Robert Siegmund

Keyword(s):

Processor Verification

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Smart diagnostics for configurable processor verification

Proceedings. 42nd Design Automation Conference, 2005. ◽

10.1109/dac.2005.193923 ◽

2005 ◽

Author(s):

S. Ezer ◽

S. Johnson

Keyword(s):

Processor Verification ◽

Configurable Processor

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Genesys-pro: innovations in test program generation for functional processor verification

IEEE Design & Test of Computers ◽

10.1109/mdt.2004.1277900 ◽

2004 ◽

Vol 21 (2) ◽

pp. 84-93 ◽

Cited By ~ 93

Author(s):

A. Adir ◽

E. Almog ◽

L. Fournier ◽

E. Marcus ◽

M. Rimon ◽

...

Keyword(s):

Test Program ◽

Program Generation ◽

Processor Verification

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Automation of Processor Verification Using Recurrent Neural Networks

2017 18th International Workshop on Microprocessor and SOC Test and Verification (MTV) ◽

10.1109/mtv.2017.15 ◽

2017 ◽

Cited By ~ 1

Author(s):

Martin Fajcik ◽

Pavel Smrz ◽

Marcela Zachariasova

Keyword(s):

Neural Networks ◽

Recurrent Neural Networks ◽

Processor Verification

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Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic

ACM Transactions on Computational Logic ◽

10.1145/371282.371364 ◽

2001 ◽

Vol 2 (1) ◽

pp. 93-134 ◽

Cited By ~ 76

Author(s):

Randal E. Bryant ◽

Steven German ◽

Miroslav N. Velev

Keyword(s):

Propositional Logic ◽

Processor Verification

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Introduction to formal processor verification at logic level

Proceedings of the 2004 workshop on Computer architecture education held in conjunction with the 31st International Symposium on Computer Architecture - WCAE '04 ◽

10.1145/1275571.1275583 ◽

2004 ◽

Author(s):

Paul Amblard ◽

Fabienne Lagnier ◽

Michel Levy

Keyword(s):

Processor Verification ◽

Logic Level

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Automatic generation of invariants in processor verification

Formal Methods in Computer-Aided Design - Lecture Notes in Computer Science ◽

10.1007/bfb0031822 ◽

1996 ◽

pp. 377-388 ◽

Cited By ~ 12

Author(s):

Jeffrey X. Su ◽

David L. Dill ◽

Clark W. Barrett

Keyword(s):

Automatic Generation ◽

Processor Verification

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Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level

10.1109/vlsi-soc53125.2021.9606997 ◽

2021 ◽

Author(s):

Frank Riese ◽

Vladimir Herdt ◽

Daniel Grose ◽

Rolf Drechsler

Keyword(s):

Metamorphic Testing ◽

Processor Verification

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