Localization of Bugs in Processor Designs Using zamiaCAD Framework

2012 ◽  
Author(s):  
Anton Tepurov ◽  
Valentin Tihhomirov ◽  
Maksim Jenihhin ◽  
Jaan Raik ◽  
Gunter Bartsch ◽  
...  
Keyword(s):  
Processor Designs

scholarly journals NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution

2012 ◽  
Vol 2012 ◽  
pp. 1-12 ◽  
Author(s):  
Kaveh Aasaraai ◽  
Andreas Moshovos
Keyword(s):  
High Efficiency ◽  
Main Memory ◽  
Data Cache ◽  
Improve Performance ◽  
Data Caches ◽  
Content Addressable Memories ◽  
Processor Designs ◽  
Level Parallelism ◽  
Order Execution ◽  
Runahead Execution

Soft processors often use data caches to reduce the gap between processor and main memory speeds. To achieve high efficiency, simple, blocking caches are used. Such caches are not appropriate for processor designs such as Runahead and out-of-order execution that require nonblocking caches to tolerate main memory latencies. Instead, these processors use non-blocking caches to extract memory level parallelism and improve performance. However, conventional non-blocking cache designs are expensive and slow on FPGAs as they use content-addressable memories (CAMs). This work proposes NCOR, an FPGA-friendly non-blocking cache that exploits the key properties of Runahead execution. NCOR does not require CAMs and utilizes smart cache controllers. A 4 KB NCOR operates at 329 MHz on Stratix III FPGAs while it uses only 270 logic elements. A 32 KB NCOR operates at 278 Mhz and uses 269 logic elements.

An SFS Berger check prediction ALU and its application to self-checking processor designs

1992 ◽  
Vol 11 (4) ◽  
pp. 525-540 ◽  
Author(s):  
J.-C. Lo ◽  
S. Thanawastien ◽  
T.R.N. Rao ◽  
M. Nicolaidis
Keyword(s):  
Processor Designs
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