On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling

2005 Sixth International Workshop on Microprocessor Test and Verification ◽

10.1109/mtv.2005.15 ◽

2005 ◽

Cited By ~ 14

Author(s):

Nicola Bombieri ◽

Andrea Fedeli ◽

Franco Fummi

Keyword(s):

Design Flow ◽

Transaction Level Modeling ◽

Transaction Level

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Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling

Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05. ◽

10.1109/memcod.2005.1487922 ◽

2005 ◽

Cited By ~ 1

Author(s):

N. Bombieri ◽

A. Fedeli ◽

F. Fummi

Keyword(s):

Design Flow ◽

Transaction Level Modeling ◽

Transaction Level

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Introducing Energy and Area Estimation in HW/SW Design Flow Based on Transaction Level Modeling

2006 International Conference on Microelectronics ◽

10.1109/icm.2006.373297 ◽

2006 ◽

Cited By ~ 3

Author(s):

Muhammad Omer Cheema ◽

Omar Hammami

Keyword(s):

Design Flow ◽

Transaction Level Modeling ◽

Area Estimation ◽

Transaction Level

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Accelerating multi-party scheduling for transaction-level modeling

Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09 ◽

10.1145/1531542.1531619 ◽

2009 ◽

Cited By ~ 2

Author(s):

Di Wang ◽

Vyas Venkataraman ◽

Zhen Wang ◽

Wei Qin ◽

Hangsheng Wang ◽

...

Keyword(s):

Transaction Level Modeling ◽

Transaction Level

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A Transaction Level Modeling of Network-on-Chip Architecture for Energy Estimation

2007 IEEE International Conference on Research, Innovation and Vision for the Future ◽

10.1109/rivf.2007.369136 ◽

2007 ◽

Cited By ~ 1

Author(s):

Anh-Vu Dinh-Duc ◽

Pascal Vivet ◽

Alain Clouard

Keyword(s):

Network On Chip ◽

Energy Estimation ◽

Transaction Level Modeling ◽

Transaction Level ◽

On Chip

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Transaction Level Modeling for Early Verification on Embedded System Design

2009 Eighth IEEE/ACIS International Conference on Computer and Information Science ◽

10.1109/icis.2009.41 ◽

2009 ◽

Cited By ~ 3

Author(s):

Maman Abdurohman ◽

Kuspriyanto K. ◽

Sarwono Sutikno ◽

Arif Sasongko

Keyword(s):

Embedded System ◽

System Design ◽

Embedded System Design ◽

Transaction Level Modeling ◽

Transaction Level

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Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Design Automation for Embedded Systems ◽

10.1007/s10617-006-9586-7 ◽

2005 ◽

Vol 10 (2-3) ◽

pp. 105-125 ◽

Cited By ~ 9

Author(s):

Nagu Dhanwada ◽

Reinaldo A. Bergamaschi ◽

William W. Dungan ◽

Indira Nair ◽

Paul Gramann ◽

...

Keyword(s):

Power Analysis ◽

Transaction Level Modeling ◽

Transaction Level

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SystemC Transaction Level Modeling and Verification of IEEE 802.15.3 MAC

2006 International Conference on Communications, Circuits and Systems ◽

10.1109/icccas.2006.285195 ◽

2006 ◽

Cited By ~ 1

Author(s):

Yu Wei ◽

He Guanghui ◽

Xu Ningyi ◽

Zhou Zucheng

Keyword(s):

Transaction Level Modeling ◽

Ieee 802.15.3 ◽

Transaction Level

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Transaction level modeling

Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04 ◽

10.1145/1016720.1016742 ◽

2004 ◽

Cited By ~ 64

Author(s):

Adam Donlin

Keyword(s):

Transaction Level Modeling ◽

Transaction Level

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CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse

Lecture Notes in Computer Science - Computational Science and Its Applications – ICCSA 2007 ◽

10.1007/978-3-540-74484-9_14 ◽

2007 ◽

pp. 154-168

Author(s):

Lilian Janin ◽

Doug Edwards

Keyword(s):

Transaction Level Modeling ◽

Transaction Level ◽

Ip Reuse

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Transaction Level Modeling

Electronic System Level Design ◽

10.1007/978-1-4020-9940-3_3 ◽

2011 ◽

pp. 25-36 ◽

Cited By ~ 2

Author(s):

Sandro Rigo ◽

Bruno Albertini ◽

Rodolfo Azevedo

Keyword(s):

Transaction Level Modeling ◽

Transaction Level

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