Low cost 10 gigabit/s optical interconnects for parallel processing

2002 ◽  
Author(s):  
D.M. Kuchta ◽  
J. Crow ◽  
P. Pepeljugoski ◽  
K. Stawiasz ◽  
J. Trewhella ◽  
...  
Keyword(s):  
Parallel Processing ◽  
Optical Interconnects ◽  
Low Cost

Active components for ultra-low-cost optical interconnects

2005 ◽  
Author(s):  
Torsten Wipiejewski ◽  
Ben Lui ◽  
Eric Tong ◽  
Kin Yau ◽  
Vincent Hung ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
Low Cost ◽  
Active Components

Optical interconnects for parallel processing

1991 ◽  
Author(s):  
Aloke Guha ◽  
Julian P. G. Bristow ◽  
Charles T. Sullivan ◽  
Anis Husain
Keyword(s):  
Parallel Processing ◽  
Optical Interconnects

Parallel Processing Creates a Low‐Cost Growth Path

1987 ◽  
Vol 5 (2) ◽  
pp. 19-25
Author(s):  
Alex Shekhel ◽  
Eva Freeman
Keyword(s):  
Parallel Processing ◽  
Low Cost ◽  
Growth Path ◽  
Cost Growth

scholarly journals A V-Shape Optical Pin Interface for Board Level Optical Interconnect

2018 ◽  
Vol 10 (1) ◽  
pp. 20
Author(s):  
Nur Najahatul Huda Saris ◽  
Osamu Mikami ◽  
Azura Hamzah ◽  
Sumiaty Ambran ◽  
Chiemi Fujikawa
Keyword(s):  
Optical Networks ◽  
Optical Interconnects ◽  
Printed Circuit Boards ◽  
Data Centers ◽  
Low Cost ◽  
Optical Interconnection ◽  
Surface Mount Technology ◽  
Optical Surface ◽  
Printed Wiring Board ◽  
Surface Mount

This paper introduces a new interface of an optical pin for Printed Circuit Boards (PCBs), the V-shape cut type which is an innovation from the 90-degree cut type optical pin. The effectiveness is determined by optical characteristics through OptiCAD and by experiment. The simulation used a model of ray tracing analysis which is a one to two (split) connection function model. For the experiment, a Polymer Optical Fibre (POF) V-shape optical pin has been fabricated. It was found that the V-shaped optical pin has a multi-branched function and is applicable to optical interconnection. Full Text: PDF ReferencesMikami, O., et al. Optical pin interface for 90-deg optical path conversion coupling to Printed Wiring Board. in Region 10 Conference (TENCON), 2016 IEEE. 2016. IEEE. CrossRef DeCusatis, C., Data center architectures, in Optical Interconnects for Data Centers. 2017, Elsevier. p. 3-41. CrossRef Duranton, M., D. Dutoit, and S. Menezo, Key requirements for optical interconnects within data centers, in Optical Interconnects for Data Centers. 2017, Elsevier. p. 75-94. CrossRef ITOH, Y., et al., Optical Coupling Characteristics of Optical Pin with 45° Micro Mirror for Optical Surface Mount Technology. Journal of The Japan Institute of Electronics Packaging, 2001. 4(6): p. 497-503. CrossRef Uchida, T. and O. Mikami, Optical surface mount technology. IEICE Transactions on Electronics, 1997. 80(1): p. 81-87. CrossRef Papakonstantinou, I., et al., Low-cost, precision, self-alignment technique for coupling laser and photodiode arrays to polymer waveguide arrays on multilayer PCBs. IEEE Transactions on Advanced Packaging, 2008. 31(3): p. 502-511. CrossRef Nakama, K., et al., Optical connection device. 2006, Google Patents. DirectLink Ramaswami, R., K. Sivarajan, and G. Sasaki, Optical networks: a practical perspective. 2009: Morgan Kaufmann. DirectLink Tong, X.C., Advanced materials for integrated optical waveguides. 2014: Springer. CrossRef

Performance comparison of 850-nm and 1550-nm VCSELs exploiting OOK, OFDM, and 4-PAM over SMF/MMF links for low-cost optical interconnects

2013 ◽  
Vol 19 (3) ◽  
pp. 206-212 ◽  
Author(s):  
Fotini Karinou ◽  
Lei Deng ◽  
Roberto Rodes Lopez ◽  
Kamau Prince ◽  
Jesper Bevensee Jensen ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
Low Cost ◽  
Performance Comparison

scholarly journals Ultra-Low Cost High-Density Two-Dimensional Visible-Light Optical Interconnects

2019 ◽  
Vol 37 (13) ◽  
pp. 3305-3314 ◽  
Author(s):  
Nikolaos Bamiedakis ◽  
Jonathan J. D. McKendry ◽  
Enyuan Xie ◽  
Erdan Gu ◽  
Martin D. Dawson ◽  
...  
Keyword(s):  
Visible Light ◽  
Optical Interconnects ◽  
Low Cost ◽  
High Density ◽  
Two Dimensional

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

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