Parallel Processing Creates a Low‐Cost Growth Path

1987 ◽  
Vol 5 (2) ◽  
pp. 19-25
Author(s):  
Alex Shekhel ◽  
Eva Freeman
Keyword(s):  
Parallel Processing ◽  
Low Cost ◽  
Growth Path ◽  
Cost Growth

Low-cost growth of AlN using vectored-flow epitaxy for the purpose of water sterilisation in a rural environment

2008 ◽  
Vol 5 (2) ◽  
pp. 559-562 ◽  
Author(s):  
Matthew Branch ◽  
Mike Robinson ◽  
Glyn Jones ◽  
Nigel Mason ◽  
Jim Dixon
Keyword(s):  
Low Cost ◽  
Rural Environment ◽  
Cost Growth

scholarly journals Low-cost growth of III–V layers on si using close-spaced vapor transport

2015 ◽  
Author(s):  
Jason W. Boucher ◽  
Ann L. Greenaway ◽  
Andrew J. Ritenour ◽  
Allison L. Davis ◽  
Benjamin F. Bachman ◽  
...  
Keyword(s):  
Low Cost ◽  
Vapor Transport ◽  
Cost Growth

Topical Review: Pathways toward cost-effective single-junction III-V solar cells

2021 ◽  
Author(s):  
Vidur Raj ◽  
Tuomas Haggren ◽  
Wei Wen Wong ◽  
Hark Hoe Tan ◽  
Chennupati Jagadish
Keyword(s):  
Solar Cells ◽  
Low Cost ◽  
Cost Effective ◽  
Device Fabrication ◽  
Topical Review ◽  
Current State ◽  
Cost Growth ◽  
Subsequent Discussion ◽  
Bandgap Semiconductors ◽  
The Cost

Abstract III-V semiconductors such as InP and GaAs are direct bandgap semiconductors with significantly higher absorption compared to silicon. The high absorption allows for the fabrication of thin/ultra-thin solar cells, which in turn permits for the realization of lightweight, flexible, and highly efficient solar cells that can be used in many applications where rigidity and weight are an issue, such as electric vehicles, the internet of things, space technologies, remote lighting, portable electronics, etc. However, their cost is significantly higher than silicon solar cells, making them restrictive for widespread applications. Nonetheless, they remain pivotal for the continuous development of photovoltaics. Therefore, there has been a continuous worldwide effort to reduce the cost of III-V solar cells substantially. This topical review summarises current research efforts in III-V growth and device fabrication to overcome the cost barriers of III-V solar cells. We start the review with a cost analysis of the current state-of-art III-V solar cells followed by a subsequent discussion on low-cost growth techniques, substrate reuse, and emerging device technologies. We conclude the review emphasizing that to substantially reduce the cost-related challenges of III-V photovoltaics, low-cost growth technologies need to be combined synergistically with new substrate reuse techniques and innovative device designs.

Versatile Metal Oxide Nanowire Devices Achieved via Controlled Doping

2007 ◽  
Vol 1018 ◽  
Author(s):  
Eric Dattoli ◽  
Qing Wan ◽  
Wei Lu
Keyword(s):  
Field Effect ◽  
Large Scale ◽  
Performance Metrics ◽  
Low Cost ◽  
Thin Film Transistor ◽  
High Electron ◽  
Glass Substrates ◽  
Sno2 Nanowires ◽  
Cost Growth

AbstractWe report on studies of field-effect transistor (FET) and transparent thin-film transistor (TFT) devices based on lightly Ta-doped SnO2 nanowires. Uniform device performance was obtained using an in situ doping method, with average field-effect mobilities exceeding 100 cm2/(V•s). Prototype fully-transparent TFT devices on glass substrates showed excellent performance metrics in terms of transconductance and on/off ratio. The combined advantages of SnO2 nanowires: namely a low cost growth process, high electron mobility, and optical transparency; make the system well suited for large-scale transparent electronics on low-temperature substrates.

scholarly journals Distribution, composition and functions of gelatinous tissues in deep-sea fishes

2017 ◽  
Vol 4 (12) ◽  
pp. 171063 ◽  
Author(s):  
Mackenzie E. Gerringer ◽  
Jeffrey C. Drazen ◽  
Thomas D. Linley ◽  
Adam P. Summers ◽  
Alan J. Jamieson ◽  
...  
Keyword(s):  
Deep Sea ◽  
Low Cost ◽  
Ionic Composition ◽  
Extracellular Fluid ◽  
Fish Locomotion ◽  
Cost Growth ◽  
Locomotory Performance ◽  
Distribution Composition ◽  
Almost All ◽  
And Function

Many deep-sea fishes have a gelatinous layer, or subdermal extracellular matrix, below the skin or around the spine. We document the distribution of gelatinous tissues across fish families (approx. 200 species in ten orders), then review and investigate their composition and function. Gelatinous tissues from nine species were analysed for water content (96.53 ± 1.78% s.d.), ionic composition, osmolality, protein (0.39 ± 0.23%), lipid (0.69 ± 0.56%) and carbohydrate (0.61 ± 0.28%). Results suggest that gelatinous tissues are mostly extracellular fluid, which may allow animals to grow inexpensively. Further, almost all gelatinous tissues floated in cold seawater, thus their lower density than seawater may contribute to buoyancy in some species. We also propose a new hypothesis: gelatinous tissues, which are inexpensive to grow, may sometimes be a method to increase swimming efficiency by fairing the transition from trunk to tail. Such a layer is particularly prominent in hadal snailfishes (Liparidae); therefore, a robotic snailfish model was designed and constructed to analyse the influence of gelatinous tissues on locomotory performance. The model swam faster with a watery layer, representing gelatinous tissue, around the tail than without. Results suggest that the tissues may, in addition to providing buoyancy and low-cost growth, aid deep-sea fish locomotion.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

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