Decentralized NIC-Switching Architecture Using SR-IOV PCI Express Network Device

IEEE Micro ◽  
2014 ◽  
Vol 34 (5) ◽  
pp. 42-50
Author(s):  
Dawei Zang ◽  
Zheng Cao ◽  
Zhan Wang ◽  
Xiaoli Liu ◽  
Lin Wang ◽  
...  
Keyword(s):  
Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.


Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1139
Author(s):  
Mykola Beshley ◽  
Natalia Kryvinska ◽  
Halyna Beshley ◽  
Oleg Yaremko ◽  
Julia Pyrih

A virtual router model with a static and dynamic resource reconfiguration for future internet networking was developed. This technique allows us to create efficient virtual devices with optimal parameters (queue length, queue overflow management discipline, number of serving devices, mode of serving devices) to ensure the required level of quality of service (QoS). An analytical model of a network device with virtual routers is proposed. By means of the mentioned mathematical representation, it is possible to determine the main parameters of the virtual queue system, which are based on the first in, first out (FIFO) algorithm, in order to analyze the efficiency of network resources utilization, as well as to determine the parameters of QoS flows, for a given intensity of packets arrival at the input interface of the network element. In order to research the guaranteed level of QoS in future telecommunications networks, a simulation model of a packet router with resource virtualization was developed. This model will allow designers to choose the optimal parameters of network equipment for the organization of virtual routers, which, in contrast to the existing principle of service, will provide the necessary quality of service provision to end users in the future network. It is shown that the use of standard static network device virtualization technology is not able to fully provide a guaranteed level of QoS to all present flows in the network by the criterion of minimum delay. An approach for dynamic reconfiguration of network device resources for virtual routers has been proposed, which allows more flexible resource management at certain points in time depending on the input load. Based on the results of the study, it is shown that the dynamic virtualization of the network device provides a guaranteed level of QoS for all transmitted flows. Thus, the obtained results confirm the feasibility of using dynamic reconfiguration of network device resources to improve the quality of service for end users.


2013 ◽  
Vol 464 ◽  
pp. 365-368 ◽  
Author(s):  
Ji Jun Hung ◽  
Kai Bu ◽  
Zhao Lin Sun ◽  
Jie Tao Diao ◽  
Jian Bin Liu

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.


2012 ◽  
Vol 229-231 ◽  
pp. 1543-1546
Author(s):  
Xiao Bo Zhou ◽  
Min Xia ◽  
Hai Long Cheng

To improve data transmission performance of the data acquisition card, a design of high-speed data transmission system is proposed in the thesis. Using FPGA of programmable logic devices, adopting Verilog HDL of hardware description language, the design of modularization and DMA transmission method is implemented in FPGA. Eventually the design implements the data transmission with high-speed through PCI Express interface. Through simulation and verification based on hardware system, this design is proved to be feasible and can satisfy the performance requirements of data transmission in the high-speed data acquisition card applied in high-speed railway communication. The design also has some value of application and reference for a universal data acquisition card.


Author(s):  
Brice Ekane ◽  
Tu Dinh Ngoc ◽  
Boris Teabe ◽  
Daniel Hagimont ◽  
Noel De Palma

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