Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability

Xiaoyao Liang; Ramon Canal; Gu-Yeon Wei; David Brooks

doi:10.1109/mm.2008.12

Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability

IEEE Micro ◽

10.1109/mm.2008.12 ◽

2008 ◽

Vol 28 (1) ◽

pp. 60-68 ◽

Cited By ~ 22

Author(s):

Xiaoyao Liang ◽

Ramon Canal ◽

Gu-Yeon Wei ◽

David Brooks

Keyword(s):

Data Cache ◽

Process Variability ◽

L1 Data

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Circuit design of a dual-versioning L1 data cache

Integration ◽

10.1016/j.vlsi.2011.11.015 ◽

2012 ◽

Vol 45 (3) ◽

pp. 237-245 ◽

Cited By ~ 1

Author(s):

Azam Seyedi ◽

Adrià Armejach ◽

Adrián Cristal ◽

Osman S. Unsal ◽

Ibrahim Hur ◽

...

Keyword(s):

Circuit Design ◽

Data Cache ◽

L1 Data

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L1 data cache decomposition for energy efficiency

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) ◽

10.1109/lpe.2001.945364 ◽

2002 ◽

Cited By ~ 1

Author(s):

Michael Huang ◽

J. Renau ◽

Seung-Moon Yoo ◽

J. Torrellas

Keyword(s):

Energy Efficiency ◽

Data Cache ◽

L1 Data

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Processor shield for L1 data cache software-based on-line self-testing

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2017.7858359 ◽

2017 ◽

Cited By ~ 1

Author(s):

Ching-Wen Lin ◽

Chung-Ho Chen

Keyword(s):

Data Cache ◽

L1 Data ◽

Self Testing ◽

On Line

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Enhancing GPU Performance by Efficient Hardware-Based and Hybrid L1 Data Cache Bypassing

Journal of Computing Science and Engineering ◽

10.5626/jcse.2017.11.2.69 ◽

2017 ◽

Vol 11 (2) ◽

pp. 69-77

Author(s):

Yijie Huangfu ◽

Wei Zhang

Keyword(s):

Data Cache ◽

L1 Data

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Compressed L1 data cache and L2 cache in GPGPUs

2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP) ◽

10.1109/asap.2016.7760766 ◽

2016 ◽

Cited By ~ 3

Author(s):

Ehsan Atoofian

Keyword(s):

Data Cache ◽

L1 Data ◽

L2 Cache

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pCache: An Observable L1 Data Cache Model for FPGA Prototyping of Embedded Systems

2013 Euromicro Conference on Digital System Design ◽

10.1109/dsd.2013.19 ◽

2013 ◽

Author(s):

Parthasarathy Ravishankar ◽

Samar Abdi

Keyword(s):

Embedded Systems ◽

Data Cache ◽

L1 Data

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L1 data cache decomposition for energy efficiency

ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581) ◽

10.1145/383082.383086 ◽

2001 ◽

Cited By ~ 28

Author(s):

Michael Huang ◽

Jose Renau ◽

Seung-Moon Yoo ◽

Josep Torrellas

Keyword(s):

Energy Efficiency ◽

Data Cache ◽

L1 Data

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Guidelines to design parity protected write-back L1 data cache

Proceedings of the 52nd Annual Design Automation Conference on - DAC '15 ◽

10.1145/2744769.2744846 ◽

2015 ◽

Cited By ~ 7

Author(s):

Yohan Ko ◽

Reiley Jeyapaul ◽

Youngbin Kim ◽

Kyoungwoo Lee ◽

Aviral Shrivastava

Keyword(s):

Data Cache ◽

L1 Data

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A Locality-Aware Write Filter Cache for Energy Reduction of STTRAM-Based L1 Data Cache

JSTS Journal of Semiconductor Technology and Science ◽

10.5573/jsts.2016.16.1.080 ◽

2016 ◽

Vol 16 (1) ◽

pp. 80-90 ◽

Cited By ~ 1

Author(s):

Joonho Kong

Keyword(s):

Energy Reduction ◽

Data Cache ◽

L1 Data

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MOESIL: A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache

10.1109/ds-rt52167.2021.9576135 ◽

2021 ◽

Author(s):

Arun S. Nair ◽

Aboli Vijayan Pai ◽

Biju K. Raveendran ◽

Geeta Patil

Keyword(s):

Data Cache ◽

L1 Data ◽

Cache Coherency ◽

Mixed Criticality

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