pCache: An Observable L1 Data Cache Model for FPGA Prototyping of Embedded Systems

2013 ◽  
Author(s):  
Parthasarathy Ravishankar ◽  
Samar Abdi
Keyword(s):  
Embedded Systems ◽  
Data Cache ◽  
L1 Data

Circuit design of a dual-versioning L1 data cache

Integration ◽  
2012 ◽  
Vol 45 (3) ◽  
pp. 237-245 ◽  
Author(s):  
Azam Seyedi ◽  
Adrià Armejach ◽  
Adrián Cristal ◽  
Osman S. Unsal ◽  
Ibrahim Hur ◽  
...  
Keyword(s):  
Circuit Design ◽  
Data Cache ◽  
L1 Data

scholarly journals Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability

IEEE Micro ◽  
2008 ◽  
Vol 28 (1) ◽  
pp. 60-68 ◽  
Author(s):  
Xiaoyao Liang ◽  
Ramon Canal ◽  
Gu-Yeon Wei ◽  
David Brooks
Keyword(s):  
Data Cache ◽  
Process Variability ◽  
L1 Data

A Buffered Dual-Access-Mode Scheme Designed for Low-Power Highly-Associative Caches

2013 ◽  
Vol 4 (2) ◽  
pp. 50-61
Author(s):  
Yul Chu ◽  
Marven Calagos
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Access Time ◽  
Data Cache ◽  
Instruction Cache ◽  
Prediction Mode ◽  
Access Mode ◽  
Cache Scheme ◽  
Better Than

This paper proposes a buffered dual-access-mode cache to reduce power consumption for highly-associative caches in modern embedded systems. The proposed scheme consists of a MRU (most recently used) buffer table and a single cache structure to implement two accessing modes, phased mode and way-prediction mode. The proposed scheme shows better access time and lower power consumption than two popular low-power caches, phased cache and way-prediction cache. The authors used Cacti and SimpleScalar simulators to evaluate the proposed cache scheme by using SPEC benchmark programs. The experimental results show that the proposed cache scheme improves the EDP (energy delay product) up to 40% for instruction cache and up to 42% for data cache compared to way-prediction cache, which performs better than phased cache.

Sign in / Sign up

Export Citation Format

Share Document