Leakage Power Analysis and Reduction for Nanoscale Circuits

IEEE Micro ◽  
2006 ◽  
Vol 26 (2) ◽  
pp. 68-80 ◽  
Author(s):  
A. Agarwal ◽  
S. Mukhopadhyay ◽  
A. Raychowdhury ◽  
K. Roy ◽  
C.H. Kim
Keyword(s):  
Power Analysis ◽  
Leakage Power ◽  
Nanoscale Circuits

Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits

2005 ◽  
Vol 52 (5) ◽  
pp. 980-986 ◽  
Author(s):  
K. Kim ◽  
K.K. Das ◽  
R.V. Joshi ◽  
C.T. Chuang
Keyword(s):  
Power Analysis ◽  
Leakage Power ◽  
Double Gate

Leakage power analysis and reduction: models, estimation and tools

2005 ◽  
Vol 152 (3) ◽  
pp. 353 ◽  
Author(s):  
A. Agarwal ◽  
S. Mukhopadhyay ◽  
C.H. Kim ◽  
A. Raychowdhury ◽  
K. Roy
Keyword(s):  
Power Analysis ◽  
Leakage Power

scholarly journals Design of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA

2019 ◽  
Vol 8 (12S2) ◽  
pp. 27-30
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Voltage Supply ◽  
Field Programmable ◽  
Eda Tools

In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

Leakage power analysis and reduction for nano-scale circuits

2011 ◽  
pp. 415-448 ◽  
Author(s):  
Amit Agarwal ◽  
Saibal Mukhopadhyay ◽  
Chris Kim ◽  
Arijit Raychowdhury ◽  
Kaushik Roy
Keyword(s):  
Power Analysis ◽  
Leakage Power ◽  
Nano Scale

Gate Leakage Power Analysis for a Nanoscale N-MOSFET

2008 ◽  
Vol 5 (11) ◽  
pp. 2180-2185
Author(s):  
Ashwani Kumar ◽  
S. Dasgupta
Keyword(s):  
Power Analysis ◽  
Leakage Power ◽  
Gate Leakage

scholarly journals Leakage Power Analysis of Domino XOR Gate

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
A. K. Pandey ◽  
R. A. Mishra ◽  
R. K. Nagaria
Keyword(s):  
Power Consumption ◽  
Threshold Voltage ◽  
Power Analysis ◽  
Leakage Power ◽  
Xor Gate ◽  
Active Mode ◽  
Hybrid Topology ◽  
Threshold Voltages ◽  
Low Threshold ◽  
Simulation Parameters

Two new XOR gates are proposed. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. Simulation parameters are measured at 25°C and 110°C. First proposed circuit reduces leakage power consumption up to 50% at 25°C and 58% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 14% as compared to standard N-type domino XOR gate. Similarly, second proposed circuit reduces leakage power consumption up to 73% at 25°C and 90% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 39% as compared to standard N-type domino XOR gate.

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